Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.

Abstract: A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)). Based on an external charger connection or disconnection, a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Abstract: The present disclosure relates to a method and a layout generation system for generating dynamic User Interface (UI) layout for an electronic device. The method includes identifying one or more operations related to at least one UI element based on a current state of a display screen of the electronic device, calculating a saliency score and an aesthetic score for each of a plurality of grids determined on the display screen, based on the calculated saliency score and the calculated aesthetic score, identifying a plurality of candidate regions, identifying an optimal region from the plurality of candidate regions based on a user interaction score and generating the dynamic UI layout by performing the one or more operations related to the at least one UI element in the optimal region.

Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.

Abstract: A software and hardware architecture framework utilize the specifications of Universal Serial Bus (USB) Type-C and Power Deliver (PD) to provide fine grain throttling of a processor (e.g., system-on-chip (SoC)). Based on an external charger connection or disconnection, a low latency fine grain power budget loss or gain indication to the processor is delivered. The mechanism of various embodiments is also applicable to connection or disconnection of VBUS powered peripheral devices to the system. The net power loss or gain available to the SoC and System is proportionally used to scale the processor throttling.

Abstract: Write performance of a block-based multi-level cell non-volatile memory is increased through the use of an internal copy of blocks with a high validity. Write (program) performance for sequential workloads is increased by moving the data in blocks with a high validity within a NAND device directly from the portion of the NAND device configured as single level cell NAND to the portion of the NAND device configured as multi-level cell NAND.

Abstract: Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a data server environment based at least in part on host managed hotness data. For example, a memory controller includes logic to receive a plurality of read and write requests from a host, where the plurality of read and write requests include an associated hotness data. A valid unit count of operational memory cells is maintained on a block-by-block basis for a plurality of memory blocks. A hotness index count is also maintained based at least in part on the hotness data on a block-by-block basis for the plurality of memory blocks. One or more memory blocks of the plurality of memory blocks are selected for eviction from a single level cell region to an x-level cell region based at least in part on the valid unit count and the hotness index count.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.

Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.

Abstract: Techniques for performing background refresh for storage devices using a timestamp from the host are described. In one example, a method involves receiving a timestamp from a host, storing the timestamp in a storage device, and determining a retention time for data stored in one or more blocks of the storage device based on the timestamp relative to a second timestamp indicating when the data was written to the one or more blocks. In response to determining the retention time exceeds a threshold, the storage device moves the data to one or more other blocks of the storage device, which can include interleaving the refresh writes with activity from the host.

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Abstract: An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.

Abstract: A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Abstract: Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

Abstract: The present disclosure relates to a method and a layout generation system for generating dynamic User Interface (UI) layout for an electronic device. The method includes identifying one or more operations related to at least one UI element based on a current state of a display screen of the electronic device, calculating a saliency score and an aesthetic score for each of a plurality of grids determined on the display screen, based on the calculated saliency score and the calculated aesthetic score, identifying a plurality of candidate regions, identifying an optimal region from the plurality of candidate regions based on a user interaction score and generating the dynamic UI layout by performing the one or more operations related to the at least one UI element in the optimal region.