Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

Abstract: A reconfigurable storage bin for a vehicle includes a storage bin portion including a base wall, a plurality of side walls including a first end wall, a second end wall opposite the first end wall, a first lateral side wall, and a second lateral side wall. The base wall and the plurality of side walls defining a storage zone. A rail member has a first end arranged at the first end wall, a second end arranged at the second end wall, and an intermediate portion extending between the first end and the second end. The intermediate portion extending at a non-zero angle relative to the first end wall, the second end wall, the first lateral side wall, and the second lateral side wall. A retaining device is mounted to the rail member. The retaining device is shiftable between the first end and the second end.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

Abstract: A storage bin for a vehicle includes a bin portion including storage volume defined by a plurality of walls including a base wall, a first side wall, a second side wall, a first end wall, and a second end wall, and a base member arranged in the storage volume. The base member is selectively height adjustable relative to the base wall.

Abstract: A reconfigurable storage bin for a vehicle includes a storage bin portion including a base wall, a plurality of side walls including a first end wall, a second end wall opposite the first end wall, a first lateral side wall, and a second lateral side wall. The base wall and the plurality of side walls defining a storage zone. A rail member has a first end arranged at the first end wall, a second end arranged at the second end wall, and an intermediate portion extending between the first end and the second end. The intermediate portion extending at a non-zero angle relative to the first end wall, the second end wall, the first lateral side wall, and the second lateral side wall. A retaining device is mounted to the rail member. The retaining device is shiftable between the first end and the second end.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and a threshold voltage mitigation circuit. The threshold voltage mitigation circuit may include a long p-channel device for producing a reference current for the current source transistors. The mitigation circuit also includes an autozero transistor and a sampling transistor for passing a global control voltage to the current source transistors. The global control voltage may be generated using a control voltage generator that includes current mirroring circuits and a replica of the current source transistors and the threshold voltage mitigation circuit.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and a threshold voltage mitigation circuit. The threshold voltage mitigation circuit may include a long p-channel device for producing a reference current for the current source transistors. The mitigation circuit also includes an autozero transistor and a sampling transistor for passing a global control voltage to the current source transistors. The global control voltage may be generated using a control voltage generator that includes current mirroring circuits and a replica of the current source transistors and the threshold voltage mitigation circuit.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and active clamping circuitry. The active clamping circuitry may be configured to sample a reset voltage and to selectively pull down the column line after a charge transfer operation if the column line exceeds the previously sampled reset voltage. The active clamping circuitry can reduce settling time during low light conditions while eliminate column fixed pattern noise.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and active clamping circuitry. The active clamping circuitry may be configured to sample a reset voltage and to selectively pull down the column line after a charge transfer operation if the column line exceeds the previously sampled reset voltage. The active clamping circuitry can reduce settling time during low light conditions while eliminate column fixed pattern noise.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a respective column output line. Each column output line may be coupled to readout circuitry that includes an adjustable current source, sample and hold circuitry, and slew rate sensing and current source control circuitry. To decrease the settling time of the column output line, the slew rate sensing and current source control circuitry may increase the magnitude of a bias current provided by the adjustable current source when the slew rate of the output voltage is above a threshold. When the slew rate of the output voltage is below the threshold, the bias current may revert to a lower magnitude to conserve power.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a respective column output line. Each column output line may be coupled to readout circuitry that includes an adjustable current source, sample and hold circuitry, and slew rate sensing and current source control circuitry. To decrease the settling time of the column output line, the slew rate sensing and current source control circuitry may increase the magnitude of a bias current provided by the adjustable current source when the slew rate of the output voltage is above a threshold. When the slew rate of the output voltage is below the threshold, the bias current may revert to a lower magnitude to conserve power.