Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and a threshold voltage mitigation circuit. The threshold voltage mitigation circuit may include a long p-channel device for producing a reference current for the current source transistors. The mitigation circuit also includes an autozero transistor and a sampling transistor for passing a global control voltage to the current source transistors. The global control voltage may be generated using a control voltage generator that includes current mirroring circuits and a replica of the current source transistors and the threshold voltage mitigation circuit.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and a threshold voltage mitigation circuit. The threshold voltage mitigation circuit may include a long p-channel device for producing a reference current for the current source transistors. The mitigation circuit also includes an autozero transistor and a sampling transistor for passing a global control voltage to the current source transistors. The global control voltage may be generated using a control voltage generator that includes current mirroring circuits and a replica of the current source transistors and the threshold voltage mitigation circuit.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and active clamping circuitry. The active clamping circuitry may be configured to sample a reset voltage and to selectively pull down the column line after a charge transfer operation if the column line exceeds the previously sampled reset voltage. The active clamping circuitry can reduce settling time during low light conditions while eliminate column fixed pattern noise.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.

Abstract: An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and active clamping circuitry. The active clamping circuitry may be configured to sample a reset voltage and to selectively pull down the column line after a charge transfer operation if the column line exceeds the previously sampled reset voltage. The active clamping circuitry can reduce settling time during low light conditions while eliminate column fixed pattern noise.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a respective column output line. Each column output line may be coupled to readout circuitry that includes an adjustable current source, sample and hold circuitry, and slew rate sensing and current source control circuitry. To decrease the settling time of the column output line, the slew rate sensing and current source control circuitry may increase the magnitude of a bias current provided by the adjustable current source when the slew rate of the output voltage is above a threshold. When the slew rate of the output voltage is below the threshold, the bias current may revert to a lower magnitude to conserve power.

Abstract: An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a respective column output line. Each column output line may be coupled to readout circuitry that includes an adjustable current source, sample and hold circuitry, and slew rate sensing and current source control circuitry. To decrease the settling time of the column output line, the slew rate sensing and current source control circuitry may increase the magnitude of a bias current provided by the adjustable current source when the slew rate of the output voltage is above a threshold. When the slew rate of the output voltage is below the threshold, the bias current may revert to a lower magnitude to conserve power.

Abstract: An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a split successive approximation register (SAR) analog-to-digital converter (ADC). The split SAR ADC may include a coarse section and a fine section. During a reset sampling phase, a reset level is sampled with a predetermined pedestal value is applied to the coarse and fine sections. During reset conversion, a reset code is obtained. During a signal sampling phase, a signal level is sampled using inverted bits of the reset code for only the fine section. During signal conversion, a signal code is obtained. Operated in this way, differential non-linearity of the ADC is minimized.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may comprise an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may comprise an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for an analog-to-digital converter (ADC). The ADC may convert an analog signal to a digital signal utilizing a two-phase conversion process to convert the signal into coarse bits and fine bits. The ADC may generate a time-residue signal and utilize the time-residue signal to determine the fine bits.

Abstract: A seat climate control system includes a seat body having a first body surface and a second body surface opposite and spaced apart from the first body surface. The seat body defines an interior volume. The seat climate control system further includes at least one thermoelectric module at least partially disposed within the interior volume of the seat body. The thermoelectric module is configured to facilitate heat transfer upon receipt of electrical energy. The seat climate control system further includes at least one thermally conductive member disposed along the first body surface. The thermally conductive member is thermally coupled to the thermoelectric module. The thermally conductive member is configured to transfer heat between the thermoelectric module and a surface in contact with the thermally conductive member.

Abstract: A seat climate control system includes a seat body having a first body surface and a second body surface opposite and spaced apart from the first body surface. The seat body defines an interior volume. The seat climate control system further includes at least one thermoelectric module at least partially disposed within the interior volume of the seat body. The thermoelectric module is configured to facilitate heat transfer upon receipt of electrical energy. The seat climate control system further includes at least one thermally conductive member disposed along the first body surface. The thermally conductive member is thermally coupled to the thermoelectric module. The thermally conductive member is configured to transfer heat between the thermoelectric module and a surface in contact with the thermally conductive member.