Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

Abstract: An analog switch includes a MOSFET that serves as a switching transistor through which the signal received at an input terminal of the analog switch passes to an output terminal of the analog switch. A resistor is coupled to the gate of the switching transistor to prevent the discharge of gate capacitance when a control signal is activating the switching transistor in an ON state. A second MOSFET has its source and drain terminals coupled across the gate and substrate of the switching transistor. The second MOSFET is activated to an ON state to provide low-impedance driving of the switching transistor when the control signal is driving the switching transistor to an OFF state. The switching MOSFET and the second MOSFET may be NMOS devices in some embodiments, while in other embodiments, PMOS devices.

Abstract: A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor.

Abstract: A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor.

Abstract: Electrostatic discharge protection for analog switches using silicon-controlled rectifiers. Two silicon-controlled rectifiers (SCRs) may be formed in a common isolation region of an integrated circuit. Each SCR has its gate and cathode coupled together so as to be self triggering. The SCRs are connected in parallel in reverse polarity and coupled between the analog switch input or output and ground. In normal switch operation, both SCRs will be off, though when the voltage of the protected switch connection exceed on of the supply rails, one of the SCRs will trigger, providing a low impedance connection to ground. Once the voltage returns to normal, the SCR will automatically release.

Abstract: A constant gate drive metal-oxide semiconductor ("MOS") analog switch. In one embodiment, the analog switch includes first, second, and third devices, and a level shifter. The first device includes a source coupled to an input terminal, a drain coupled to an output terminal, and a gate. The second device includes a source coupled to the input terminal, a drain, and a gate. The third device includes a source coupled to the drain of the second device, a drain coupled to the output terminal, and a gate. The level shifter includes an input coupled to the drain of the second device and an output coupled to the gates of the first, second, and third devices. The level shifter provides a constant gate drive to the first device, regardless of a signal on the input terminal, resulting in a constant on-resistance of the analog switch. In addition, a constant linearity of on-resistance is achieved by keeping the gate voltage constant with respect to the mid-point of the source and drain voltages.