Patents by Inventor Shankar Venkataraman

Shankar Venkataraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods of modifying interlayer adhesion
    Patent number: 8569166
    Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Francimar Campana Schmitt, Li-Qun Xia, Son Van Nguyen, Shankar Venkataraman
  • PRETREATMENT AND IMPROVED DIELECTRIC COVERAGE
    Publication number: 20130252440
    Abstract: Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance.
    Type: Application
    Filed: September 20, 2012
    Publication date: September 26, 2013
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Lei Luo, Shankar Venkataraman, Manuel A. Hernandez, Kedar Sapre, Zhong Qiang Hua
  • Loadlock batch ozone cure
    Patent number: 8524004
    Abstract: A substrate processing chamber for processing a plurality of wafers in batch mode. In one embodiment the chamber includes a vertically aligned housing having first and second processing areas separated by an internal divider, the first processing area positioned directly over the second processing area; a multi-zone heater operatively coupled to the housing to heat the first and second processing areas independent of each other; a wafer transport adapted to hold a plurality of wafers within the processing chamber and move vertically between the first and second processing areas; a gas distribution system adapted to introduce ozone into the second area and steam into the first processing area; and a gas exhaust system configured to exhaust gases introduced into the first and second processing areas.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 3, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Jay D. Pinson, II, Kirby H. Floyd, Adib Khan, Shankar Venkataraman
  • Integrated process modulation for PSG gapfill
    Patent number: 8497211
    Abstract: A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: July 30, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Young S. Lee, Anchuan Wang, Lan Chia Chan, Shankar Venkataraman
  • Preferential dielectric gapfill
    Patent number: 8476142
    Abstract: Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 2, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Sasha Kweskin, Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman, Kadar Sapre
  • Post-planarization densification
    Patent number: 8466067
    Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • SURFACE TREATMENT AND DEPOSITION FOR REDUCED OUTGASSING
    Publication number: 20130149462
    Abstract: A method of forming a dielectric layer is described. The method first deposits a silicon-nitrogen-and-hydrogen-containing (polysilazane) layer by radical-component chemical vapor deposition (CVD). The silicon-nitrogen-and-hydrogen-containing layer is formed by combining a radical precursor (excited in a remote plasma) with an unexcited carbon-free silicon precursor. A silicon oxide capping layer may be formed from a portion of the carbon-free silicon-nitrogen-and-hydrogen-containing layer to avoid time-evolution of underlying layer properties prior to conversion into silicon oxide. Alternatively, the silicon oxide capping layer is formed over the silicon-nitrogen-and-hydrogen-containing layer. Either method of formation involves the formation of a local plasma within the substrate processing region.
    Type: Application
    Filed: June 12, 2012
    Publication date: June 13, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Jingmei Liang, Xiaolin Chen, Nitin K. Ingle, Shankar Venkataraman
  • Invertable pattern loading with dry etch
    Patent number: 8435902
    Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jing Tang, Nitin Ingle, Dongqing Yang, Shankar Venkataraman
  • SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA
    Publication number: 20130082197
    Abstract: Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Jang-Gyoo Yang, Matthew L. Miller, Xinglong Chen, Kien N. Chuc, Qiwei Liang, Shankar Venkataraman, Dmitry Lubomirsky
  • DOUBLE PATTERNING ETCHING PROCESS
    Publication number: 20130048605
    Abstract: A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: Applied Materials, Inc.
    Inventors: Kedar SAPRE, Jing Tang, Ajay Bhatnagar, Nitin Ingle, Shankar Venkataraman
  • INSTANTANEOUS DECODER REFRESH FRAME ALIGNED MULTI-BITRATE TRANSCODER OUTPUT
    Publication number: 20130044803
    Abstract: A video stream is transcoded to provide a plurality of primary profiles. Individual frames of the video stream have a Presentation Time Stamp (PTS). A PTS is used as a token to identify particular frames to be encoded as Instantaneous Decoder Refresh (IDR) frames in each profile. An IDR frame period is determined, indicative of a desired number of video frames between two IDR frames. An IDR frame is inserted into each profile every IDR frame period. The IDR frames of each profile are aligned with the same IDR frames of the other profiles. The PTS of each IDR frame in each profile is monitored. Upon determining that a PTS is out of alignment, the next PTS of the affected profile is aligned with the corresponding PTS of remaining profiles. Backup transcoders produce backup profiles that are maintained in alignment with each other and with the primary profiles.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: RGB Networks, Inc.
    Inventors: Yuval Fisher, Hain-Ching Liu, Dan R. Hunt, Shankar Venkataraman, Hsiang-Yun Alex Huang
  • INTEGRATED PROCESS MODULATION FOR PSG GAPFILL
    Publication number: 20120325773
    Abstract: A method of depositing a phosphosilicate glass (PSG) film on a substrate disposed in a substrate processing chamber includes depositing a first portion of the PSG film over the substrate using a high-density plasma process. Thereafter, a portion of the first portion of the PSG film may be etched back. The etch back process may include flowing a halogen precursor to the substrate processing chamber, forming a high-density plasma from the halogen precursor, and terminating flowing the halogen precursor after the etch back. The method also includes flowing a halogen scavenger to the substrate processing chamber to react with residual halogen in the substrate processing chamber, and exposing the first portion of the PSG film to a phosphorus-containing gas to provide a substantially uniform phosphorus concentration throughout the first portion of the PSG film.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 27, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Young S. Lee, Anchuan Wang, Lan Chia Chan, Shankar Venkataraman
  • Post-planarization densification
    Patent number: 8329587
    Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: December 11, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • In-situ ozone cure for radical-component CVD
    Patent number: 8304351
    Abstract: Methods of forming a dielectric layer are described. The methods include the steps of mixing a silicon-containing precursor with a plasma effluent, and depositing a silicon-and-nitrogen-containing layer on a substrate. The silicon-and-nitrogen-containing layer is converted to a silicon-and-oxygen-containing layer by curing in an ozone-containing atmosphere in the same substrate processing region used for depositing the silicon-and-nitrogen-containing layer. Another silicon-and-nitrogen-containing layer may be deposited on the silicon-and-oxygen-containing layer and the stack of layers may again be cured in ozone all without removing the substrate from the substrate processing region. After an integral multiple of dep-cure cycles, the conversion of the stack of silicon-and-oxygen-containing layers may be annealed at a higher temperature in an oxygen-containing environment.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: November 6, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Linlin Wang, Abhijit Basu Mallick, Nitin K. Ingle, Shankar Venkataraman
  • TWO-STAGE OZONE CURE FOR DIELECTRIC FILMS
    Publication number: 20120238108
    Abstract: A method of forming a silicon oxide layer is described. The method increases the oxygen content of a dielectric layer by curing the layer in a two-step ozone cure. The first step involves exposing the dielectric layer to ozone while the second step involves exposing the dielectric layer to ozone excited by a local plasma. This sequence can reduce or eliminate the need for a subsequent anneal following the cure step. The two-step ozone cures may be applied to silicon-and-nitrogen-containing film to convert the films to silicon oxide.
    Type: Application
    Filed: September 7, 2011
    Publication date: September 20, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Xiaolin Chen, Jingmei Liang, Nitin K. Ingle, Shankar Venkataraman
  • REDUCED PATTERN LOADING USING SILICON OXIDE MULTI-LAYERS
    Publication number: 20120225565
    Abstract: Aspects of the disclosure pertain to methods of depositing conformal silicon oxide multi-layers on patterned substrates. The conformal silicon oxide multi-layers are each formed by depositing multiple sub-layers. Sub-layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS) and an oxygen-containing precursor into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. A plasma treatment may follow formation of sub-layers to further improve conformality and to decrease the wet etch rate of the conformal silicon oxide multi-layer film. The deposition of conformal silicon oxide multi-layers grown according to embodiments have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
    Type: Application
    Filed: October 3, 2011
    Publication date: September 6, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Sidharth Bhatia, Paul Edward Gee, Shankar Venkataraman
  • Reduced pattern loading using bis(diethylamino)silane (CHNSi) as silicon precursor
    Patent number: 8236708
    Abstract: Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 7, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
  • SEMICONDUCTOR PROCESSING SYSTEM AND METHODS USING CAPACITIVELY COUPLED PLASMA
    Publication number: 20120180954
    Abstract: Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
    Type: Application
    Filed: October 3, 2011
    Publication date: July 19, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Jang-Gyoo Yang, Matthew L. Miller, Xinglong Chen, Kien N. Chuc, Qiwei Liang, Shankar Venkataraman, Dmitry Lubomirsky
  • LOADLOCK BATCH OZONE CURE
    Publication number: 20120145079
    Abstract: A substrate processing chamber for processing a plurality of wafers in batch mode. In one embodiment the chamber includes a vertically aligned housing having first and second processing areas separated by an internal divider, the first processing area positioned directly over the second processing area; a multi-zone heater operatively coupled to the housing to heat the first and second processing areas independent of each other; a wafer transport adapted to hold a plurality of wafers within the processing chamber and move vertically between the first and second processing areas; a gas distribution system adapted to introduce ozone into the second area and steam into the first processing area; and a gas exhaust system configured to exhaust gases introduced into the first and second processing areas.
    Type: Application
    Filed: June 15, 2011
    Publication date: June 14, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Jay D. Pinson, II, Kirby H. Floyd, Adib Khan, Shankar Venkataraman
  • HEATER WITH INDEPENDENT CENTER ZONE CONTROL
    Publication number: 20120103970
    Abstract: A substrate heater comprising a ceramic substrate support having a substantially flat upper surface for supporting a substrate during substrate processing; a resistive heater embedded within the substrate support; a heater shaft coupled to a back surface of the substrate support, the heater having an interior cavity that extends along its longitudinal axis and ends at a bottom central surface of the substrate support; and a supplemental heater, separate from the ceramic substrate support, positioned within the interior cavity of the heater shaft in thermal contact with a portion of the bottom central surface of the substrate support such that the supplemental heater can alter the temperature of a central area of the upper surface of the substrate support.
    Type: Application
    Filed: May 2, 2011
    Publication date: May 3, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Dmitry Lubomirsky, Sudhir R. Gondhalekar, Shankar Venkataraman, Kirby H. Floyd, Yizhen Zhang