Abstract: The present invention is a method and apparatus for cleaning a chemical vapor deposition (CVD) chamber using cleaning gas energized to a plasma in a gas mixing volume separated by an electrode from a reaction volume of the chamber. In one embodiment, a source of RF power is coupled to a lid of the chamber, while a switch is used to couple a showerhead to ground terminals or the source of RF power.

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract: Method, system, and computer program product to enforce application dependencies, by building a data model based on inputs specifying relationships between a plurality of applications, generating, based on the data model, a list of candidate executions for a first application having a specified relationship with a second application, and outputting a visual representation of the data model, the visual representation comprising a plurality of objects representing the plurality of applications and arranged to represent the relationships between the applications, the list of candidate executions, and one or more user interface elements allowing user navigation between the first application and the second application, of the list of candidate executions.

Abstract: Method, system, and computer program product to enforce application dependencies, by building a data model based on inputs specifying relationships between a plurality of applications, generating, based on the data model, a list of candidate executions for a first application having a specified relationship with a second application, and outputting a visual representation of the data model, the visual representation comprising a plurality of objects representing the plurality of applications and arranged to represent the relationships between the applications, the list of candidate executions, and one or more user interface elements allowing user navigation between the first application and the second application, of the list of candidate executions.

Abstract: Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.

Abstract: Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

Abstract: A wafer chuck assembly includes a puck, a shaft and a base. An insulating material defines a top surface of the puck, a heater element is embedded within the insulating material, and a conductive plate lies beneath the insulating material. The shaft includes a housing coupled with the plate, and electrical connectors for the heater elements and the electrodes. A conductive base housing couples with the shaft housing, and the connectors pass through a terminal block within the base housing. A method of plasma processing includes loading a workpiece onto a chuck having an insulating top surface, providing a DC voltage differential across two electrodes within the top surface, heating the chuck by passing current through heater elements, providing process gases in a chamber surrounding the chuck, and providing an RF voltage between a conductive plate beneath the chuck, and one or more walls of the chamber.

Abstract: A method of forming a dielectric layer is described. The method first deposits a silicon-nitrogen-and-hydrogen-containing (polysilazane) layer by radical-component chemical vapor deposition (CVD). The silicon-nitrogen-and-hydrogen-containing layer is formed by combining a radical precursor (excited in a remote plasma) with an unexcited carbon-free silicon precursor. A silicon oxide capping layer may be formed from a portion of the carbon-free silicon-nitrogen-and-hydrogen-containing layer to avoid time-evolution of underlying layer properties prior to conversion into silicon oxide. Alternatively, the silicon oxide capping layer is formed over the silicon-nitrogen-and-hydrogen-containing layer. Either method of formation involves the formation of a local plasma within the substrate processing region.

Abstract: A method of etching doped silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using partial remote plasma excitation. The remote plasma excites a fluorine-containing precursor and the plasma effluents created are flowed into a substrate processing region. A hydrogen-containing precursor, e.g. water, is concurrently flowed into the substrate processing region without plasma excitation. The plasma effluents are combined with the unexcited hydrogen-containing precursor in the substrate processing region where the combination reacts with the doped silicon oxide. The plasmas effluents react with the patterned heterogeneous structures to selectively remove doped silicon oxide.

Abstract: One example includes a fragmented video transcoding system. The system includes a video fragmenter configured to receive a linear input video data feed and to generate a plurality of video fragment files corresponding to separate portions of the linear input video data feed. The system also includes a transcoder system configured to encode the plurality of video fragment files to generate a plurality of transcoded video fragment files to be accessible for delivery to at least one client device.

Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.

Abstract: Semiconductor processing systems are described including a process chamber. The process chamber may include a lid assembly, grid electrode, conductive insert, and ground electrode. Each component may be coupled with one or more power supplies operable to produce a plasma within the process chamber. Each component may be electrically isolated through the positioning of a plurality of insulation members. The one or more power supplies may be electrically coupled with the process chamber with the use of switching mechanisms. The switches may be switchable to electrically couple the one or more power supplies to the components of the process chamber.

Abstract: Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region.

Abstract: A substrate processing system that has a plurality of deposition chambers, and one or more robotic arms for moving a substrate between one or more of a deposition chamber, load lock holding area, and a curing and treatment module. The substrate curing and treatment module is attached to the load-lock substrate holding area, and may include: The curing chamber for curing a dielectric layer in an atmosphere comprising ozone, and a treatment chamber for treating the cured dielectric layer in an atmosphere comprising water vapor. The chambers may be vertically aligned, have one or more access doors, and may include a heating system to adjust the curing and/or heating chambers between two or more temperatures respectively.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: Methods of forming air gaps in a 3-d flash memory cell using only gas-phase etching techniques are described. The methods include selectively gas-phase etching tungsten deposited into the stack structure to separate the tungsten levels. Other metals than tungsten may be used. The methods also include selectively etching silicon oxide from between the tungsten levels to make room for vertically spaced air gaps. A nonconformal silicon oxide layer is then deposited to trap the air gaps. Both tungsten removal and silicon oxide removal use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. The nonconformal silicon oxide may be deposited inside or outside the mainframe.

Abstract: Methods of etching back shallow trench isolation (STI) dielectric and trimming the exposed floating gate without breaking vacuum are described. The methods include recessing silicon oxide dielectric gapfill to expose vertical sidewalls of polysilicon floating gates. The exposed vertical sidewalls are then isotropically etched to evenly thin the polysilicon floating gates on the same substrate processing mainframe. Both recessing silicon oxide and isotropically etching polysilicon use remotely excited fluorine-containing apparatuses attached to the same mainframe to facilitate performing both operations without an intervening atmospheric exposure. An inter-poly dielectric may then be conformally deposited either on the same mainframe or outside the mainframe.