Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output voltage with controlled ripple current. The buck converter may include one or more main buck converter stages and one or more suppression buck converter stages coupled with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents to reduce ripple currents generated in the one or main buck converter stages.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.

Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.

Abstract: Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

Abstract: In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.

Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Abstract: Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.

Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

Abstract: Systems and methods are provided for adaptive configuration and control of digital-to-analog converters (DACs). Performance of a plurality of conversion elements in a digital-to-analog converter (DAC) may be assessed based on particular input conditions associated with a digital input to the DAC, and the DAC may be configured based on the assessing of performance. Each conversion element of the plurality of conversion elements handles a particular bit in the digital input. The configuring may comprise selecting a subset of the plurality of conversion elements, and setting only the subset of the plurality of conversion elements to apply a particular type of operations. The particular type of operations pertains to applying digital-to-analog conversions via the DAC, and the particular type of operations relates to or affects performance. The particular input conditions may comprise signal backoff.