Patents by Inventor Shao-Hua Hsu
Shao-Hua Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113112Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20240047581Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: SHAO-HUA HSU, CHIH-WEI WU, MAO-LIN WENG, WEI-YEH TANG, YEN-CHENG LAI, CHUN-CHAN HSIAO, PO-HSIANG CHUANG, CHIH-LONG CHIANG, YIH-ANN LIN, RYAN CHIA-JEN CHEN
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Patent number: 11894370Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: August 9, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20230253479Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: ApplicationFiled: April 18, 2023Publication date: August 10, 2023Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Patent number: 11652155Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: GrantFiled: May 24, 2022Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Publication number: 20220384269Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Patent number: 11502076Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: November 30, 2018Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Publication number: 20220285530Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Publication number: 20220262920Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.Type: ApplicationFiled: May 9, 2022Publication date: August 18, 2022Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
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Patent number: 11349014Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: GrantFiled: June 30, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Patent number: 11329140Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.Type: GrantFiled: January 17, 2020Date of Patent: May 10, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
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Publication number: 20220059685Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
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Publication number: 20210408266Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
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Patent number: 11171236Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.Type: GrantFiled: October 5, 2018Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu
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Publication number: 20210280695Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: May 20, 2021Publication date: September 9, 2021Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
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Patent number: 11114549Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: GrantFiled: March 1, 2018Date of Patent: September 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen Chen, Ming-Ching Chang, Yi-Chun Chen, Yu-Hsien Lin, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu
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Publication number: 20210226033Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.Type: ApplicationFiled: January 17, 2020Publication date: July 22, 2021Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
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Patent number: 10796943Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: GrantFiled: November 6, 2018Date of Patent: October 6, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Publication number: 20200144102Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Publication number: 20200044070Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.Type: ApplicationFiled: October 5, 2018Publication date: February 6, 2020Inventors: Shiang-Bau Wang, Li-Wei Yin, Shao-Hua Hsu