Patents by Inventor Shao-Hua Hsu
Shao-Hua Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10325912Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: GrantFiled: October 30, 2017Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang
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Publication number: 20190165137Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: March 1, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ryan Chia-Jen CHEN, Ming-Ching CHANG, Yi-Chun CHEN, Yu-Hsien LIN, Li-Wei YIN, Tzu-Wen PAN, Cheng-Chung CHANG, Shao-Hua HSU
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Publication number: 20190131297Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: RYAN CHIA-JEN CHEN, LI-WEI YIN, TZU-WEN PAN, YI-CHUN CHEN, CHENG-CHUNG CHANG, SHAO-HUA HSU, YU-HSIEN LIN, MING-CHING CHANG
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Publication number: 20190131298Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.Type: ApplicationFiled: November 30, 2018Publication date: May 2, 2019Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
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Patent number: 9384962Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.Type: GrantFiled: April 7, 2011Date of Patent: July 5, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Patent number: 8999830Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: December 19, 2013Date of Patent: April 7, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8952451Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: GrantFiled: December 20, 2013Date of Patent: February 10, 2015Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140339652Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.Type: ApplicationFiled: August 1, 2014Publication date: November 20, 2014Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
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Patent number: 8841181Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.Type: GrantFiled: March 7, 2012Date of Patent: September 23, 2014Assignee: United Microelectronics Corp.Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
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Patent number: 8802524Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.Type: GrantFiled: March 22, 2011Date of Patent: August 12, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
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Publication number: 20140127892Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: ApplicationFiled: December 19, 2013Publication date: May 8, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Patent number: 8709930Abstract: A semiconductor process is provided. The prior steps include: a first gate including a first cap layer and a second gate including a second cap layer are formed on a substrate. A hard mask layer is formed to cover the first gate and the second gate. The material of the hard mask layer is different from the material of the first cap layer and the second cap layer. The hard mask layer is removed entirely after a lithography process and an etching process are performed. The following steps include: a material is formed to entirely cover the first gate and the second gate. The material, the first gate and the second gate are etched back to make the first gate and the second gate have the same level and expose layers in both of them.Type: GrantFiled: November 25, 2011Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Zen-Jay Tsai, Shao-Hua Hsu, Chi-Horn Pai, Ying-Hung Chou, Shih-Hao Su, Shih-Chieh Hsu, Chih-Ho Wang, Hung-Yi Wu, Shui-Yen Lu
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Patent number: 8704294Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.Type: GrantFiled: June 13, 2011Date of Patent: April 22, 2014Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140103443Abstract: A semiconductor device having a metal gate includes a substrate having a first gate trench and a second gate trench formed thereon, a gate dielectric layer respectively formed in the first gate trench and the second gate trench, a first work function metal layer formed on the gate dielectric layer in the first gate trench and the second gate trench, a second work function metal layer respectively formed in the first gate trench and the second gate trench, and a filling metal layer formed on the second work function metal layer. An opening width of the second gate trench is larger than an opening width of the first gate trench. An upper area of the second work function metal layer in the first gate trench is wider than a lower area of the second work function metal layer in the first gate trench.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yeng-Peng Wang, Chun-Hsien Lin, Chan-Lon Yang, Guang-Yaw Hwang, Shin-Chi Chen, Hung-Ling Shih, Jiunn-Hsiung Liao, Chia-Wen Liang
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Publication number: 20140065299Abstract: A method of making an electrode useable in an electrochemical cell, includes the steps of (a) providing an electrically conductive substrate; (b) forming nanostructured current collectors on the conductive substrate; and (c) attaching nanoparticles of a ternary orthosilicate composite to the nanostructured current collectors. The ternary orthosilicate composite includes Li2MnxFeyCozSiO4, where x+y+z=1.Type: ApplicationFiled: November 8, 2013Publication date: March 6, 2014Applicant: VANDERBILT UNIVERSITYInventors: Weng Poo Kang, Supil Raina, Shao-Hua Hsu, Siyu Wei
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Patent number: 8623555Abstract: In one aspect of the present invention, an electrode useable in an electrochemical cell includes an electrically conductive substrate, nanostructured current collectors in electrical contact with the conductive substrate, and nanoparticles of a ternary orthosilicate composite coated on the nanostructured current collectors. The ternary orthosilicate composite comprises Li2MnxFeyCozSiO4, where x+y+z=1.Type: GrantFiled: May 25, 2012Date of Patent: January 7, 2014Assignee: Vanderbilt UniversityInventors: Weng Poo Kang, Supil Raina, Shao-Hua Hsu, Siyu Wei
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Patent number: 8574990Abstract: The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.Type: GrantFiled: February 24, 2011Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Shui-Yen Lu, Pei-Yu Chou, Shin-Chi Chen, Jiunn-Hsiung Liao, Shang-Yuan Tsai, Chan-Lon Yang, Teng-Chun Tsai, Chun-Hsien Lin
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Publication number: 20130234216Abstract: A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.Type: ApplicationFiled: March 7, 2012Publication date: September 12, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ying-Hung Chou, Shao-Hua Hsu, Chi-Horn Pai, Zen-Jay Tsai, Shih-Hao Su, Chun-Chia Chen, Shih-Chieh Hsu, Chih-Chung Chen
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Patent number: 8492259Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.Type: GrantFiled: August 16, 2012Date of Patent: July 23, 2013Assignee: United Microelectronics Corp.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
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Patent number: 8486842Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.Type: GrantFiled: October 8, 2010Date of Patent: July 16, 2013Assignee: United Microelectronics Corp.Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen