Patents by Inventor Shao Liu

Shao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966822
    Abstract: Disclosed are a computer-implemented method, a system and a computer program product for feature processing. In the computer-implemented method for feature processing, two input features selected from multiple features of each sample in a sample set are projected to one resulting feature by one or more processing units based on a specified curve. The sample set is updated by replacing the two input features with the one resulting feature for each sample in the sample set by one or more processing units. The projecting and the updating for the sample set are repeated by one or more processing units until the number of features of each sample in the sample set reaches a predetermined criterion.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chun Lei Xu, Si Er Han, Shi Bin Liu, Yi Shao, Lei Tian, Hao Zheng, Jia Rui Wang
  • Publication number: 20240113233
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Leonard P. GULER, Sukru YEMENICIOGLU, Shengsi LIU, Shao Ming KOH, Tahir GHANI
  • Patent number: 11828722
    Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Yi-Shao Liu, Tung-Tsun Chen, Chan-Ching Lin, Jui-Cheng Huang, Felix Ying-Kit Tsui, Jing-Hwang Yang
  • Publication number: 20230375501
    Abstract: A method of making a biochip includes forming an opening extending completely through a fluidic substrate. Forming the opening includes defining a plurality of sidewalls on the fluidic substrate, wherein the plurality of sidewalls defines a channel in fluid communication with the opening, and each of the plurality of sidewalls comprises polydimethylsiloxane (PDMS). The method further includes coating a surface of the fluidic substrate with a silicon oxide coating wherein, the silicon oxide coating is between adjacent sidewalls of the plurality of sidewalls. The method further includes bonding the fluidic substrate to a detection substrate.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Yi-Shao LIU, Chun-Ren CHENG, Chun-Wen CHENG
  • Publication number: 20230375499
    Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chuan LIAO, Chien-Kuo YANG, Yi-Shao LIU, Tung-Tsun CHEN, Chan-Ching LIN, Jui-Cheng HUANG, Felix Ying-Kit TSUI, Jing-Hwang YANG
  • Patent number: 11824002
    Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 21, 2023
    Assignee: Intel Corporation
    Inventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu
  • Patent number: 11823602
    Abstract: A layout arrangement of a driver integrated circuit includes multiple output pads, a plurality of switching circuits, and multiple data channel circuits. The output pads include a first output pad and a second output pad and are configurable to be coupled to a plurality of data lines. The switching circuits include a first switching circuit. A first selection terminal of the first switching circuit is coupled to the first output pad via a first connecting wire. A second selection terminal of the first switching circuit is coupled to the second output pad via a second connecting wire. The data channel circuits include a first data channel circuit. An output terminal of the first data channel circuit is coupled to a common terminal of the first switching circuit via a third connecting wire. The third connecting wire is longer than the first connecting wire and the second connecting wire.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: November 21, 2023
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hsiu-Hui Yang, Yu-Shao Liu
  • Patent number: 11768170
    Abstract: A biochip including a fluidic substrate having an opening extending completely through the fluidic substrate. The biochip further includes a silicon oxide coating on the fluidic substrate. The biochip further includes a plurality of sidewalls on the fluidic substrate, wherein the plurality of sidewalls defines a channel in fluid communication with the opening, the silicon oxide coating is between adjacent sidewalls of the plurality of sidewalls, and each of the plurality of sidewalls comprises polydimethylsiloxane (PDMS). The biochip further includes a detection substrate spaced from the fluidic substrate.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Shao Liu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 11703475
    Abstract: A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes electrically connecting at least one electronic probe tip extending from the first major surface to a corresponding conductive area of the device area. The method further includes stamping a test fluid onto the device area. The method further includes measuring via the at least one electronic probe tip a first electrical property of one or more bio-FETs of the device area based on the test fluid.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Shao Liu, Fei-Lung Lai, Chun-Ren Cheng, Chun-Wen Cheng
  • Publication number: 20230081170
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Application
    Filed: October 31, 2022
    Publication date: March 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander KALNITSKY, Yi-Shao LIU, Kai-Chih LIANG, Chia-Hua CHU, Chun-Ren CHENG, Chun-Wen CHENG
  • Patent number: 11537739
    Abstract: The present application is related to system and method for analyzing confidential data. Firstly, a first key is used to obtain a first analysis authorization for proceeding a first analysis responsive to an operational model in an encrypted cloud space with a connection of a network. Then, the result of the first analysis is verified. While the verifying of the operational model is pass, a second key is used to obtain a second analysis authorization for proceeding a second analysis responsive to an operational model without the connection of the network. Thereby, the cloud technique for analyzing data can be applied for analyzing confidential data.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 27, 2022
    Assignee: National Applied Research Laboratories
    Inventors: Hsi-Ching Lin, Yu-Shao Liu, August Chao
  • Publication number: 20220387959
    Abstract: A method of operating an integrated circuit includes using a first switching device to couple a bio-sensing device to a first signal path, generating, using the bio-sensing device, a bio-sensing signal on the first signal path in response to an electrical characteristic of a sensing film, using a second switching device to couple a temperature-sensing device to a second signal path, and generating, using the temperature-sensing device, a temperature-sensing signal on the second signal path in response to a temperature of the sensing film. The first and second switching devices, the bio-sensing device, the temperature-sensing device, and the sensing film are components of a sensing pixel of a plurality of sensing pixels of the integrated circuit.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 8, 2022
    Inventors: Tung-Tsun CHEN, Yi-Shao LIU, Jui-Cheng HUANG, Chin-Hua WEN, Felix Ying-Kit TSUI, Yung-Chow PENG
  • Patent number: 11504690
    Abstract: An integrated circuit includes two or more rows of heating elements, two or more columns of heating elements, and a plurality of sensing areas. Each sensing area is between two adjacent rows of the rows of heating elements and between two adjacent columns of the columns of heating elements and includes a bio-sensing device and a temperature-sensing device.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Patent number: 11498044
    Abstract: An integrated circuit includes two or more rows of heating elements, two or more columns of heating elements, and a plurality of sensing circuits. Each sensing circuit is between two adjacent rows of the rows of heating elements and between two adjacent columns of the columns of heating elements, in a same silicon layer as the rows of heating elements and the columns of heating elements, and configured to generate a bio-sensing signal and a temperature-sensing signal.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Patent number: 11491455
    Abstract: An integrated circuit includes an interconnection structure, first and second sensing pixels over the interconnection structure, and an isolation layer over the first and second sensing pixels. Each of the first and second sensing pixels includes a bio-sensing device, a temperature-sensing device, one or more heating elements adjacent to the bio-sensing device and the temperature-sensing device, and a sensing film over the bio-sensing device. The isolation layer includes a first opening configured to expose the sensing film of the first sensing pixel without exposing the sensing film of the second sensing pixel and a second opening configured to expose the sensing film of the second sensing pixel without exposing the sensing film of the first sensing pixel.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Patent number: 11486854
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 11446630
    Abstract: An integrated circuit includes a plurality of sensing pixels, each sensing pixel including a sensing film portion, a bio-sensing device configured to generate a first signal responsive to an electrical characteristic of the sensing film portion, a first switching device coupled between the bio-sensing device and a first signal path, a temperature-sensing device configured to generate a second signal responsive to a temperature of the sensing film portion, and a second switching device coupled between the temperature-sensing device and a second signal path.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Tsun Chen, Yi-Shao Liu, Jui-Cheng Huang, Chin-Hua Wen, Felix Ying-Kit Tsui, Yung-Chow Peng
  • Publication number: 20220246077
    Abstract: A layout arrangement of a driver integrated circuit includes multiple output pads, a plurality of switching circuits, and multiple data channel circuits. The output pads include a first output pad and a second output pad and are configurable to be coupled to a plurality of data lines. The switching circuits include a first switching circuit. A first selection terminal of the first switching circuit is coupled to the first output pad via a first connecting wire. A second selection terminal of the first switching circuit is coupled to the second output pad via a second connecting wire. The data channel circuits include a first data channel circuit. An output terminal of the first data channel circuit is coupled to a common terminal of the first switching circuit via a third connecting wire. The third connecting wire is longer than the first connecting wire and the second connecting wire.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Hsiu-Hui Yang, Yu-Shao Liu
  • Patent number: 11367373
    Abstract: A driver integrated circuit, including multiple output pads, multiple switching circuits, and multiple data channel circuits, is provided. The output pads and the switching circuits are arranged in a pad area of the driver integrated circuit. The output pads include a first output pad and a second output pad, and the switching circuits include a first switching circuit. A first selection terminal of the first switching circuit is coupled to the first output pad. A second selection terminal of the first switching circuit is coupled to the second output pad. The data channel circuits are arranged in a function circuit area of the driver integrated circuit. The data channel circuits include a first data channel circuit. An output terminal of the first data channel circuit is coupled to a common terminal of the first switching circuit.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 21, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hsiu-Hui Yang, Yu-Shao Liu
  • Patent number: 11353421
    Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Shih-Wei Lin, Yi-Shao Liu