Patents by Inventor Shao Liu

Shao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190101531
    Abstract: The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 4, 2019
    Inventors: Chia-Hua Chu, Allen Timothy Chang, Ching-Ray Chen, Yi-Hsien Chang, Yi-Shao Liu, Chun-Ren Cheng, Chun-Wen Cheng
  • Publication number: 20190056348
    Abstract: A method of manufacturing an integrated circuit device includes providing a substrate comprising a semiconductor active layer, and forming source/drain regions, temperature sensors, and heating elements either in the semiconductor active layer or on the front side of the semiconductor active layer. The semiconductor active layer has channel regions between adjacent source/drain regions, and each of the heating elements is aligned over at least a portion of a corresponding temperature sensor. The method also includes forming a metal interconnect structure over the front side of the semiconductor active layer and exposing the channel regions from the back side of the semiconductor active layer substrate. A fluid gate dielectric layer is formed over the exposed channel regions.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 21, 2019
    Inventors: Yi-Shao Liu, Jui-Cheng Huang, Tung-Tsun Chen
  • Patent number: 10204999
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10184912
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Yi-Shao Liu, Fei-Lung Lai, Wei-Cheng Lin, Ta-Chuan Liao, Chien-Kuo Yang
  • Publication number: 20180374927
    Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 27, 2018
    Applicant: INTEL CORPORATION
    Inventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, CHIA-HONG Jan
  • Patent number: 10155244
    Abstract: The present disclosure relates to a micro-fluidic probe card that deposits a fluidic chemical onto a substrate with a minimal amount of fluidic chemical waste, and an associated method of operation. In some embodiments, the micro-fluidic probe card has a probe card body with a first side and a second side. A sealant element, which contacts a substrate, is connected to the second side of the probe card body in a manner that forms a cavity within an interior of the sealant element. A fluid inlet, which provides a fluid from a processing tool to the cavity, is a first conduit extending between the first side and the second side of the probe card body. A fluid outlet, which removes the fluid from the cavity, is a second conduit extending between the first side and the second side of the probe card body.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Jung-Huei Peng, Yi-Shao Liu, Fei-Lung Lai, Shang-Ying Tsai
  • Publication number: 20180350932
    Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or J-shape, for example.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 6, 2018
    Applicant: INTEL CORPORATION
    Inventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
  • Patent number: 10145847
    Abstract: The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate. Through-holes for inlet and outlet are formed in the transparent substrate or the second substrate. Various non-organic landings with support medium for bio-materials to attach are formed on the first substrate and the second substrate before they are combined. In other embodiments, the microfluidic channel is formed of an adhesion layer between a transparent substrate and a second substrate with landings on the substrates.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Allen Timothy Chang, Ching-Ray Chen, Yi-Hsien Chang, Yi-Shao Liu, Chun-Ren Cheng, Chun-Wen Cheng
  • Patent number: 10139364
    Abstract: A device layer of an integrated circuit device includes a semiconductor active layer spanning a plurality of device regions. Each of the device regions has a heating element, a temperature sensor, and bioFETs in the device layer. The bioFETs have source/drain regions and channel regions in the semiconductor active layer and fluid gates exposed on a surface for fluid interfacing on one side of the device layer. A multilayer metal interconnect structure is disposed on the opposite side of the device layer. This structure places the heating elements in proximity to the fluid gates enabling localized heating, precision heating, and multiplexed temperature control for multiplexed bio-sensing applications.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Shao Liu, Jui-Cheng Huang, Tung-Tsun Chen
  • Patent number: 10124335
    Abstract: An integrated fluidic module includes a fluid manifold, a valve stator, a valve rotor and a valve housing. The fluid manifold includes microchannels connected to a sample reaction unit, and fluid input channels connected to fluid sources. The valve stator includes at least one groove and plural through holes, at least one groove is connected with at least one of the plural through holes, and parts of the groove and through holes are communicated with the microchannels and the fluid input channels. The valve rotor includes at least one groove. The valve housing accommodates the valve rotor and the valve stator. When the valve rotor is rotated to different positions, at least one groove of the valve rotor is connected with at least one through hole or groove of the valve stator to provide at least one fluid path and enable fluids provided by the fluid sources to be directed to corresponding chambers of the sample reaction unit through the fluid path.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: November 13, 2018
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Qian Liang, Revata Utama, Yi-shao Liu
  • Publication number: 20180313783
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure, an isolation layer, an interface layer in an opening of the isolation layer, and a metal crown structure over the interface layer. The interface layer and the metal crown structure are disposed on opposite side of the transistor from a gate structure.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 1, 2018
    Inventors: Chun-Wen CHENG, Yi-Shao LIU, Fei-Lung LAI
  • Publication number: 20180293955
    Abstract: A driving integrated circuit (IC) and a fan-out compensation method thereof are provided. The driving IC includes a plurality of driving channel circuits, a plurality of output buffer circuits and a compensation control circuit. The input terminals of the output buffer circuits are coupled to the output terminals of the driving channel circuits in a one-to-one manner. The output terminals of the output buffer circuits are coupled a plurality of data lines of a display panel in a one-to-one manner. The compensation control circuit is coupled to the output buffer circuits for adjusting the slew rate of the output terminals of the output buffer circuits to compensate difference in delay times between the data lines of the display panel.
    Type: Application
    Filed: October 19, 2017
    Publication date: October 11, 2018
    Applicant: Novatek Microelectronics Corp.
    Inventor: Yu-Shao Liu
  • Patent number: 10094801
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity. An amplification factor of the BioFET device may be provided by a difference in capacitances associated with the gate structure on the first surface and with the interface layer formed on the second surface.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Yi-Shao Liu, Rashid Bashir, Fei-Lung Lai, Chun-wen Cheng
  • Publication number: 20180238827
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Chun-Wen CHENG, Yi-Shao Liu, Fei-Lung Lai, Wei-Cheng Lin, Ta-Chuan Liao, Chien-Kuo Yang
  • Patent number: 10048747
    Abstract: An image such as a depth image of a scene may be received, observed, or captured by a device. A grid of voxels may then be generated based on the depth image such that the depth image may be downsampled. A background included in the grid of voxels may also be removed to isolate one or more voxels associated with a foreground object such as a human target. A location or position of one or more extremities of the isolated human target may then be determined.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 14, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Johnny Chung Lee, Tommer Leyvand, Szymon Piotr Stachniak, Craig Peeper, Shao Liu
  • Publication number: 20180195998
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Alexander Kalnitsky, Yi-Shao Liu, Kai-Chih Liang, Chia-Hua Chu, Chun-Ren Cheng, Chun-Wen Cheng
  • Publication number: 20180195999
    Abstract: A method of sensing a biological sample includes introducing a fluid containing the biological sample through a first opening in a substrate. The method further includes passing the fluid from the first opening to a first cavity through at least one microfluidic channel. The method further includes repelling the biological sample from a first surface of the first cavity using a first surface modification layer. The method further includes attracting the biological sample to a sensing device using a plurality of modified surface patterns, wherein a first modified surface pattern of the plurality of modified surface patterns has different surface properties from a second modified surface pattern of the plurality of modified surface patterns. The method further includes outputting the fluid through a second opening in the substrate.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Inventors: Yi-Shao LIU, Chun-Wen CHENG, Chun-Ren CHENG
  • Publication number: 20180197966
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Application
    Filed: July 17, 2015
    Publication date: July 12, 2018
    Applicant: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Publication number: 20180141021
    Abstract: An integrated circuit includes two or more rows of heating elements, two or more columns of heating elements, and a plurality of sensing areas. Each sensing area is between two adjacent rows of the rows of heating elements, between two adjacent columns of the columns of heating elements, and includes a bio-sensing device and a temperature-sensing device.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 24, 2018
    Inventors: Tung-Tsun CHEN, Yi-Shao LIU, Jui-Cheng HUANG, Chin-Hua WEN, Felix Ying-Kit TSUI, Yung-Chow PENG
  • Patent number: 9976982
    Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 22, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wen Cheng, Yi-Shao Liu, Fei-Lung Lai, Wei-Cheng Lin, Ta-Chuan Liao, Chien-Kuo Yang