Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.

Abstract: Embodiments of the disclosure relate to active cooling devices for cooling an electronic assembly positioned downstream in a computing system. In one embodiment, an electronic assembly positioned downstream of the computing system is disclosed. The electronic assembly includes a printed circuit board electrically connected to the computing system; an air duct disposed over the printed circuit board; and an active cooling device thermally coupled to the printed circuit board. The printed circuit board includes a transceiver socket configured to receive at least one optical transceiver and one or more heat-generating components disposed thereon. The at least one optical transceiver is configured to mate with an active optical cable.

Abstract: A closed-loop liquid cooling system includes a liquid coolant conduit, a cold plate, a pump and a heat exchanger. The liquid coolant conduit is in proximity to a heat-generating electrical component. The liquid coolant conduit allows circulation of a liquid coolant to extract heat therefrom. The liquid coolant conduit includes an inner portion that surrounds and contains the liquid coolant, and an outer portion configured to prevent or inhibit leakage of the liquid coolant from the inner portion and also detect any leakage from the inner portion. The cold plate is in thermal communication with the liquid coolant. The pump is configured to transport the liquid coolant in the liquid coolant conduit. The heat exchanger is coupled to the liquid coolant conduit to extract heat therefrom.

Abstract: A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.

Abstract: Embodiments of the disclosure relate to active cooling devices for cooling an electronic assembly positioned downstream in a computing system. In one embodiment, an electronic assembly positioned downstream of the computing system is disclosed. The electronic assembly includes a printed circuit board electrically connected to the computing system; an air duct disposed over the printed circuit board; and an active cooling device thermally coupled to the printed circuit board. The printed circuit board includes a transceiver socket configured to receive at least one optical transceiver and one or more heat-generating components disposed thereon. The at least one optical transceiver is configured to mate with an active optical cable.

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Abstract: A chip and an interface conversion device are provided. The chip includes first, second, third, fourth, fifth and sixth pads. The first and second pads are coupled to first and second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to first and second pins of an AUX channel of a DP connector respectively. When the chip operates in a first mode, first and second AUX channel signals generated by the chip are transmitted to the third and fifth pads respectively, a voltage of the fourth pad is weakly pulled down, and a voltage of the sixth pad is weakly pulled up. When the chip operates in a second mode, one of the first and second pads is connected to the fourth pad, and the other one of the first and second pads is connected to the sixth pad.

Abstract: A chip and an interface conversion device are provided. The chip includes first, second, third, fourth, fifth and sixth pads. The first and second pads are coupled to first and second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to first and second pins of an AUX channel of a DP connector respectively. When the chip operates in a first mode, first and second AUX channel signals generated by the chip are transmitted to the third and fifth pads respectively, a voltage of the fourth pad is weakly pulled down, and a voltage of the sixth pad is weakly pulled up. When the chip operates in a second mode, one of the first and second pads is connected to the fourth pad, and the other one of the first and second pads is connected to the sixth pad.

Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.

Abstract: The present disclosure relates to a semiconductor substrate including, a first silicon layer comprising an upper surface with protrusions extending vertically with respect to the upper surface. An isolation layer is arranged over the upper surface meeting the first silicon layer at an interface, and a second silicon layer is arranged over the isolation layer. A method of manufacturing the semiconductor substrate is also provided.

Abstract: An integrated circuit includes a stacked MIM capacitor and a thin film resistor and methods of fabricating the same are disclosed. A capacitor bottom metal in one capacitor of the stacked MIM capacitor and the thin film resistor are substantially at the same layer of the integrated circuit, and the capacitor bottom metal and the thin film resistor are also made of substantially the same materials. The integrated circuit with both of a stacked MIM capacitor and a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.

Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Abstract: The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.

Abstract: According to an embodiment of the invention, an optoelectronic device is provided. The optoelectronic device includes: a lead frame having a reflective structure, wherein the reflective structure has an opening; an optoelectronic element disposed in the opening; at least one electrode disposed in the lead frame and electrically connected to the optoelectronic element; a lens disposed on the lead frame and having an adhesive portion having a holding surface, an alignment surface, and an adhesive surface, wherein the adhesive surface has a convex surface or a concave surface; and a covering adhesive layer filling a region defined by the reflective structure, covering the optoelectronic element, and adhering the lens to the lead frame through the adhesive portion of the lens.

Abstract: A light emitting device and manufacturing method thereof are disclosed. The light emitting device includes a substrate, a LED die, a first transparent layer, an optical wavelength conversion layer and a second transparent layer. The substrate has a die glue part. The LED die is disposed on the die glue part and has a base which is made of a transparent material. The first transparent layer is disposed on the side surface of the LED die. The optical wavelength conversion layer is evenly formed on the first transparent layer and the LED die. The second transparent layer is formed on the optical wavelength conversion layer.

Abstract: A lighting device includes a lighting engine and at least a wavelength-converting element. The lighting engine includes a circuit board, a blue light emitting diode and a red light emitting diode. The blue light emitting diode and a red light emitting diode are disposed on the circuit board. The wavelength-converting element covers at least the blue light emitting diode. A wavelength-converted light is generated by converting a part of light emitted by the lighting engine through the wavelength-converting element. White light having a color temperature within a range from 2580K to 3220K on the black-body radiation of the CIE-1931 chromaticity diagram is generated by mixing the wavelength-converted light and non-converted light emitted by the lighting engine.