Abstract: The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals.

Abstract: In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.

Abstract: A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: An anti-fuse array includes first through fourth adjacent anti-fuse bit columns, the anti-fuse bits of the first and second anti-fuse bit columns including portions of active areas of a first active area column, and the anti-fuse bits of the third and fourth anti-fuse bit columns including portions of active areas of a second active area column. Each row of a first set of conductive segment rows includes first and second conductive segments positioned between adjacent active areas of the first active area column and a third conductive segment positioned between adjacent active areas of the second active area column. Each row of a second set of conductive segments alternating with the first set of conductive segment rows includes a fourth conductive segment positioned between adjacent active areas of the first active area column and fifth and sixth conductive segments positioned between adjacent active areas of the second active area column.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and a first active area, and a second anti-fuse structure including a second dielectric layer between a second gate conductor and the first active area. A first via is electrically connected to the first gate conductor at a first location a first distance from the first active area, a second via is electrically connected to the second gate conductor at a second location a second distance from the first active area, and the first distance is approximately equal to the second distance.

Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

Abstract: A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

Abstract: An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.

Abstract: A memory circuit includes a sense amplifier coupled to a non-volatile memory cell, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The sense amplifier includes a comparator. The comparator includes a first input terminal coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage, a second input terminal configured to receive a second voltage, and a first output terminal configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. The detection circuit includes a first inverter. A first input terminal of the first inverter is configured to receive the first output signal. A first output terminal of the first inverter is configured to generate an inverted first output signal.