Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and a first active area, and a second anti-fuse structure including a second dielectric layer between a second gate conductor and the first active area. A first via is electrically connected to the first gate conductor at a first location a first distance from the first active area, a second via is electrically connected to the second gate conductor at a second location a second distance from the first active area, and the first distance is approximately equal to the second distance.

Abstract: An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: A layout method includes: forming a layout structure of a memory array having a first row, wherein the first row comprises a plurality of storage cells; disposing a word line; disposing a plurality of control electrodes for connecting the plurality of storage cells of the first row to the word line; and disposing a first cut layer on a first portion of a first control electrode of the plurality of control electrodes.

Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the seco

Abstract: A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.

Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A layout method includes: forming a layout structure of a memory array having a first row and a second row, wherein each of the first row and the second row comprises a plurality of storage cells; disposing a word line between the first row and the second row; disposing a plurality of control electrodes across the word line for connecting the plurality of storage cells of the first row and the plurality of storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the plurality of control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the plurality of control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

Abstract: An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

Abstract: A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.