Patents by Inventor Shaofeng Ding
Shaofeng Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250034546Abstract: The instant invention provides a deblocking double-layer chromatography and cassette for isolating nucleic acids from liquid biopsy samples such as urine with large sample volumes, small nucleic acid sizes, and low nucleic acid concentrations. Compared with the prior art of Ding et al. (U.S. Pat. No. 9,163,230) which proved the principle of double-layer chromatography comprising a positively charged DEAE membrane and a silica membrane, we further explored and optimized the membrane compositions and solution compositions for plasma and urine samples. More importantly, we set up a “deblocking” mechanism to overcome a “blocking” problem that the membrane is blocked by solid particles in the plasma and urine samples, thus greatly increasing its flowability. In addition, it omits a pre-filtering step, thus particularly suitable for its automation.Type: ApplicationFiled: July 12, 2024Publication date: January 30, 2025Inventors: Shaofeng Ding, Qiang Liu
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Patent number: 12199016Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: GrantFiled: December 5, 2023Date of Patent: January 14, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20250014968Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: September 18, 2024Publication date: January 9, 2025Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Publication number: 20250006594Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: September 16, 2024Publication date: January 2, 2025Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Publication number: 20240395672Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.Type: ApplicationFiled: August 2, 2024Publication date: November 28, 2024Applicant: Name SAMSUNG ELECTRONICS CO.,LTD.Inventors: Shaofeng DING, Sungwook MOON, Jeonghoon AHN, Yunki CHOI
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Patent number: 12107034Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.Type: GrantFiled: November 2, 2021Date of Patent: October 1, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Sungwook Moon, Jeonghoon Ahn, Yunki Choi
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Publication number: 20240234490Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Publication number: 20240222421Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.Type: ApplicationFiled: March 13, 2024Publication date: July 4, 2024Inventors: Jihyung KIM, Jeonghoon Ahn, Jaehee Oh, Shaofeng Ding, Wonji Park, Jegwan Hwang
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Publication number: 20240209428Abstract: A new fluorescence detection method called pyrophosphorolysis activated fluorescence was developed to measure PAP amplification of nucleic acid. A fluorophore-quencher-dual-labeled blocked primer was used for PAP: I) which has a fluorophore attached to a nucleotide in the internal region or at the 5? end and a quencher attached to a blocked nucleotide at the 3? end, or II) which has a quencher attached to a nucleotide in the internal region or at the 5? end and a fluorophore attached to a blocked nucleotide at the 3? end. Multiple fluorophore-quencher-dual-labeled blocked primers were also used for multiplex PAP, which are attached with different fluorophores to distinguish multiple templates in a reaction.Type: ApplicationFiled: January 29, 2024Publication date: June 27, 2024Inventors: Shaofeng Ding, Qiang Liu
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Patent number: 12014935Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.Type: GrantFiled: May 14, 2020Date of Patent: June 18, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Publication number: 20240178131Abstract: A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other, and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.Type: ApplicationFiled: October 23, 2023Publication date: May 30, 2024Inventors: Sunoo KIM, Shaofeng Ding, Jeonghoon Ahn, Jaehee Oh
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Publication number: 20240164081Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.Type: ApplicationFiled: January 5, 2024Publication date: May 16, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Shaofeng DING, Jeong Hoon AHN, Yun Ki CHOI
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Patent number: 11961882Abstract: A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.Type: GrantFiled: September 13, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11955509Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.Type: GrantFiled: December 22, 2021Date of Patent: April 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jihyung Kim, Jeonghoon Ahn, Jaehee Oh, Shaofeng Ding, Wonji Park, Jegwan Hwang
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Publication number: 20240105556Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Inventors: SHAOFENG DING, JEONG HOON AHN, YUN KI CHOI
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Patent number: 11921049Abstract: A new fluorescence detection method called pyrophosphorolysis activated fluorescence was developed to measure PAP amplification of nucleic acid. A fluorophore-quencher dual-attached blocked primer was used for PAP which has a fluorophore attached to a nucleotide in the internal region or at the 5? end and a quencher attached to a blocked nucleotide at the 3? end. Multiple fluorophore-quencher dual-labeled blocked primers were also used for multiplex PAP, which are attached with different fluorophores to distinguish multiple templates in a reaction.Type: GrantFiled: October 19, 2019Date of Patent: March 5, 2024Inventors: Shaofeng Ding, Qiang Liu
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Patent number: 11876038Abstract: A semiconductor device includes a substrate provided with an integrated circuit and a contact, an interlayer dielectric layer covering the integrated circuit and the contact, a through electrode penetrating the substrate and the interlayer dielectric layer, a first intermetal dielectric layer on the interlayer dielectric layer, and first and second wiring patterns in the first intermetal dielectric layer. The first wiring pattern includes a first conductive pattern on the through electrode, and a first via penetrating the first intermetal dielectric layer and connecting the first conductive pattern to the through electrode. The second wiring pattern includes a second conductive pattern on the contact, and a second via penetrating the first intermetal dielectric layer and connecting the second conductive pattern to the contact. A first width in a first direction of the first via is greater than a second width in the first direction of the second via.Type: GrantFiled: September 8, 2021Date of Patent: January 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11871553Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, the intermediate connection layer including a connection pattern electrically connected to the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, the etch stop layer covering a top surface of the connection pattern, and a penetration contact extended from the first metal layer toward a bottom surface of the substrate penetrating the connection region.Type: GrantFiled: September 14, 2021Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11845981Abstract: A minimal-copy-ratio of templates is a problem in detecting early stage cancer where minimal copies of somatic cancer-specific mutations are targeted in the presence of large copies of wildtype genome DNA, commonly a 1/10,000 or even less minimal-copy-ratios between the mutant target and wildtype control templates. To overcome this problem, delayed pyrophosphorolysis activated polymerization (delayed-PAP) was developed which can delay product accumulation of the wildtype control to a much later time or cycle, such as by 15 cycles or by 30,000 folds. In the multiplex format, delayed-PAP is particularly useful to amplify not only the wildtype control but also mutant target templates accurately and consistently in the minimal-copy-ratio situation.Type: GrantFiled: January 27, 2022Date of Patent: December 19, 2023Inventors: Shaofeng Ding, Qiang Liu
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Patent number: 11798883Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.Type: GrantFiled: November 16, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi