Abstract: A computerized simulation validating method for a full-scale distribution network single phase-to-ground fault test is implemented by simulating a full-scale test system with external quantities being controlled to be conformant and validating the full-scale distribution network single phase-to-ground fault test based on a conformance check result between the internal quantities of the field testing and the internal quantities of the simulation testing. The simulation validating method for a full-scale distribution network single phase-to-ground fault test improves normalization and conformance of the full-scale distribution network ground fault test. The computerized simulation validating system, apparatus, and medium for a full-scale distribution network single phase-to-ground fault test also achieve the benefits noted above.

Abstract: A system and a method for an integrated test on a primary-secondary pole-mounted breaker. The method includes: establishing an electrical connection between the system and the primary-secondary pole-mounted breaker; establishing a communication connection between the system and the primary-secondary pole-mounted breaker; applying, by the system, a voltage signal and a current signal to the primary-secondary pole-mounted breaker through the electrical connection, to generate a voltage and a current on the primary-secondary pole-mounted breaker; collecting, by the system, signals of the voltage and the current fed back from the primary-secondary pole-mounted breaker through the communication connection; performing, by the system, an integrated accuracy test and an integrated protection test; outputting a test result of the accuracy test and a test result of the integrated protection test to the industrial control machine, to generate the test report.

Abstract: A system and a method for an integrated test on a primary-secondary pole-mounted breaker. The method includes: establishing an electrical connection between the system and the primary-secondary pole-mounted breaker; establishing a communication connection between the system and the primary-secondary pole-mounted breaker; applying, by the system, a voltage signal and a current signal to the primary-secondary pole-mounted breaker through the electrical connection, to generate a voltage and a current on the primary-secondary pole-mounted breaker; collecting, by the system, signals of the voltage and the current fed back from the primary-secondary pole-mounted breaker through the communication connection; performing, by the system, an integrated accuracy test and an integrated protection test; outputting a test result of the accuracy test and a test result of the integrated protection test to the industrial control machine, to generate the test report.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The semiconductor device includes a substrate; two fins located on the substrate and extending along a first direction; an isolation material layer surrounding the fins, comprising a first isolation regions located at an end region between the two fins along the first direction, and a second isolation region located at sides of the fins along a second direction that is different from the first direction, wherein an upper surface of the first isolation region substantially align with an upper surfaces of the fins, and an upper surface of the second isolation region is lower than the upper surface of the fins; and a first insulating layer on the first isolation region.

Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a substrate, at least one source region on the substrate, an interlayer dielectric layer covering a portion of the source region and having a cavity on the source region, and a pseudo gate insulation layer at the bottom of the cavity covering a portion of the source region; forming a barrier layer in the cavity; forming a loss reduction region in the interlayer dielectric layer by conducting an ion implantation process comprising silicon ion or carbon ion; removing the barrier layer; removing the pseudo gate insulation layer to expose a portion of the source region; and forming a gate structure on the exposed portion of the source region. This inventive concept reduces the loss of the interlayer dielectric layer, thus reduces the height loss of the gate electrode.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor.

Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.

Abstract: A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

Abstract: A fin-type field effect transistor includes a semiconductor body formed on a substrate, the semiconductor body having a top surface and a pair of laterally opposite sidewalls, and a gate electrode formed above the sidewalls and the top surface of the semiconductor body. The semiconductor body further includes a source region formed on an end portion of the semiconductor body, a drain region formed on another end portion of the semiconductor body, and a channel region formed between the source region and the drain region and surrounded by the gate electrode, wherein a doping concentration of the channel region decreases with increasing distance from the top surface and the sidewalls.

Abstract: An electric connector, a plug-in module thereof and a production method of the plug-in module are provided. The plug-in module comprises a base, an input unit, an output unit and an output end. The base comprises a top plate, a bottom plate and one connection plate. A plurality of input terminals and a plurality of intermediate terminals are fixed to the base. The input unit comprises one input circuit board provided vertically to the base and electrically coupled to an end portion of the input terminals. At least one channel are provided on the input circuit board. Each channel comprises a transformer electrically coupled to the input circuit board. The output unit comprises an output circuit board horizontally provided to the base and electrically coupled to the input circuit board via the intermediate terminals. The output end are fixed to and electrically coupled to the output circuit board.

Abstract: A method of manufacturing a fin-type field effect transistor includes sequentially forming a first mask and a second mask on a semiconductor substrate; patterning the second mask; forming and patterning a third mask on the second mask in accordance with a fin pattern of the fin-type field effect transistor; etching the semiconductor substrate, the first mask, and the second mask through the third mask, wherein portions of the first and second masks are removed and a first trench is formed in the semiconductor substrate; removing the third mask; etching the first mask through the second mask and removing the second mask; etching the semiconductor substrate through the first mask to form a plurality of fins and a second trench disposed between adjacent fins, wherein etching the semiconductor substrate further deepens the first trench such that a depth of the first trench is greater than a depth of the second trench.

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

Abstract: A method for DRC verification of a design layout file comprising off-grid patterns includes identifying an off-grid pattern having one or more off-grid sides, outwardly expanding the one or more off-grid sides to adjacent grids to obtain a first on-grid pattern, inwardly contracting the expanded one or more sides of the first on-grid pattern to adjacent grids to obtain a second on-grid pattern, and performing a DRC verification on the second on-grid pattern using an existing on-grid DRC deck. The method also includes making a backup copy of the design layout file prior to converting the identified off-grid pattern into an on-grid pattern.

Abstract: A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

Abstract: An electric connector, a plug-in module thereof and a production method of the plug-in module are provided. The plug-in module comprises a base, an input unit, an output unit and an output end. The base comprises a top plate, a bottom plate and one connection plate. A plurality of input terminals and a plurality of intermediate terminals are fixed to the base. The input unit comprises one input circuit board provided vertically to the base and electrically coupled to an end portion of the input terminals. At least one channel are provided on the input circuit board. Each channel comprises a transformer electrically coupled to the input circuit board. The output unit comprises an output circuit board horizontally provided to the base and electrically coupled to the input circuit board via the intermediate terminals. The output end are fixed to and electrically coupled to the output circuit board.

Abstract: A method of manufacturing a fin-type field effect transistor includes sequentially forming a first mask and a second mask on a semiconductor substrate; patterning the second mask; forming and patterning a third mask on the second mask in accordance with a fin pattern of the fin-type field effect transistor; etching the semiconductor substrate, the first mask, and the second mask through the third mask, wherein portions of the first and second masks are removed and a first trench is formed in the semiconductor substrate; removing the third mask; etching the first mask through the second mask and removing the second mask; etching the semiconductor substrate through the first mask to form a plurality of fins and a second trench disposed between adjacent fins, wherein etching the semiconductor substrate further deepens the first trench such that a depth of the first trench is greater than a depth of the second trench.

Abstract: A method of manufacturing a semiconductor CMOS device is provided. The method includes providing a semiconductor substrate, forming a first fin in a PMOS region and a second fin in an NMOS region of the semiconductor substrate, forming shallow trench isolation structures on the semiconductor substrate on opposite sides of the first and second fins, and performing ion implantation so as to implant germanium atoms into the first fin to form a silicon-germanium layer in the PMOS region. The silicon-germanium layer is used to adjust a work function of the PMOS region. The method further includes forming a stack structure in the PMOS region and the NMOS region, whereby the stack structure comprises a work function layer and a metal gate.