Patents by Inventor Shaofeng Yu

Shaofeng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080265344
    Abstract: A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Freidoon Mehrad, Shaofeng Yu, Steven A. Vitale, Joe G. Tran
  • Publication number: 20080265420
    Abstract: A method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate (the gate stack comprising a polysilicon layer and a blocking layer), and performing an ion implantation into an active region of the substrate adjacent to the gate stack (the blocking layer substantially blocks the ion implantation from the polysilicon layer).
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaofeng Yu, Freidoon Mehrad, Jiong-Ping Lu
  • Patent number: 7435638
    Abstract: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: October 14, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Shyh-Horng Yang
  • Patent number: 7416949
    Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 26, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Francis Pas, Shaofeng Yu
  • Publication number: 20080191289
    Abstract: Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.
    Type: Application
    Filed: February 14, 2007
    Publication date: August 14, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Michael Francis Pas, Shaofeng Yu
  • Publication number: 20080176345
    Abstract: Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.
    Type: Application
    Filed: January 19, 2007
    Publication date: July 24, 2008
    Inventors: Shaofeng Yu, Richard L. Guldi, Jiong-Ping Lu, Freidoon Mehrad, Jae Hyun Park
  • Patent number: 7396716
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: July 8, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Freidoon Mehrad, Shaofeng Yu, Joe G. Tran
  • Publication number: 20080157258
    Abstract: A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Steven Arthur Vitale, Shaofeng Yu
  • Patent number: 7341933
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: March 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Haowen Bu, Jiong-Ping Lu, Lindsey Hall
  • Patent number: 7338888
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: March 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Haowen Bu, Shaofeng Yu, Ping Jiang
  • Publication number: 20070275517
    Abstract: Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 29, 2007
    Inventors: Shaofeng Yu, Shyh-Horng Yang
  • Patent number: 7253049
    Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Shaofeng Yu, Haowen Bu, Lindsey H. Hall, Mark R. Visokay
  • Publication number: 20070170464
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: March 8, 2007
    Publication date: July 26, 2007
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Publication number: 20070161246
    Abstract: A method for removing dielectric material 50 from a semiconductor wafer 20 that contains metal silicide 60 or 90. The method includes performing a selective etch 202 of the semiconductor wafer 20 using an organic semi-aqueous solvent-based etchant until the dielectric material 50 is substantially removed and then rinsing 204 the semiconductor wafer 20 including a surface, 63 or 93, of the metal silicide, 60 or 90 respectively, of the semiconductor wafer 20.
    Type: Application
    Filed: May 10, 2006
    Publication date: July 12, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Yaw Obeng, Jiong-Ping Lu, Shaofeng Yu
  • Patent number: 7231463
    Abstract: In one embodiment of the invention, a Peer-to-Peer (P2P) subsystem includes a cache of a current peer and a peer locator. The current peer is in a current ring at a current level. The cache stores information of ring peers within the current ring. The current ring is part of a hierarchical ring structure of P2P nodes. The hierarchical ring structure has at least one of a lower level and a upper level. The peer locator locates a target peer in the cache in response to a request.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Gururaj Nagendra, Shaofeng Yu
  • Patent number: 7229871
    Abstract: A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: June 12, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Benjamin P. McKee
  • Patent number: 7223679
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: May 29, 2007
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Publication number: 20070099407
    Abstract: A method for making a transistor 20 that includes performing a low temperature spike anneal 314. The method also includes performing a silicide anneal 318 to fully silicide the gate electrode 90 of the transistor 20. A blocking layer 120 protects the source and drain regions 60 of the transistor 20 during the processes of low temperature spike anneal 3.14 and silicide anneal 318.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 3, 2007
    Inventors: Jiong-Ping Lu, Shaofeng Yu
  • Publication number: 20070063294
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
    Type: Application
    Filed: November 6, 2006
    Publication date: March 22, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haowen Bu, Jiong-Ping Lu, Shaofeng Yu, Ping Jiang, Clint Montgomery
  • Patent number: 7189627
    Abstract: A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: March 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiqiang Wu, Shaofeng Yu, C. Rinn Cleavelin