Abstract: Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.

Abstract: Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing transfer margin information.

Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system. An illustrative data processing system includes a processing circuit that processes unprocessed codewords, and provides failed codewords when the processing fails to converge. The system may further include an input buffer circuit that selectively stores a combination of at least one of the unprocessed codewords and at least one of the failed codewords. The input buffer circuit includes a first portion that maintains any of the unprocessed codewords and the failed codewords, and a second portion that maintains only the failed codewords.

Abstract: An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.

Abstract: A system includes a first sync mark detector circuit operable to apply a first sync mark detection algorithm to search a received media sector and overhead for a second sync mark after a failure to identify a first sync mark. A second sync mark detector circuit operable to apply a second sync mark detection algorithm to search the received media sector and overhead for the second sync mark. An anchor point identification circuit identifies an anchor point in the received media sector. A retry controller circuit causes a re-read of the received media sector and overhead when the first sync mark detector circuit fails to identify the first sync mark, and aligns the received media sector to yield an aligned media sector. A data processing circuit recovers an original user data set from the aligned media sector.

Abstract: An apparatus for processing data includes a data detector configured to detect data values in data sectors to yield detected data, a data decoder configured to decode the detected data, wherein the data detector and the data decoder are configured to process the data sectors in a series of global iterations, a memory configured to store parity sector soft information, and a scheduler configured to control overlapping reprocessing of a failed sector in the data detector and the data decoder based on the parity sector soft information with processing of another data sector in the data detector and the data decoder.

Abstract: Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.

Abstract: An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.

Abstract: Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing non-standard bus information.

Abstract: Systems and methods relating generally to data processing, and more particularly to adjusting gain parameters in relation to data processing.

Abstract: An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a parity check matrix with non-uniform column weights, and at least one scaling circuit configured to scale values in the data decoding circuit with a scaling value that is dependent at least in part on a column weight of the likelihood values being scaled.

Abstract: An apparatus includes a storage medium operable to store a number of data tracks, a read channel circuit operable to process the data tracks read from the storage medium, and a track quality classifier circuit operable to determine a track quality metric for the data tracks read from the storage medium. The track quality metric indicates whether a corresponding one of the data tracks that has failed to successfully process in the read channel circuit can be reprocessed within a track gap period.

Abstract: An apparatus for processing data includes a data detector configured to detect data values in data sectors to yield detected data, a data decoder configured to decode the detected data, wherein the data detector and the data decoder are configured to process the data sectors in a series of global iterations, a memory configured to store parity sector soft information, and a scheduler configured to control overlapping reprocessing of a failed sector in the data detector and the data decoder based on the parity sector soft information with processing of another data sector in the data detector and the data decoder.

Abstract: An apparatus includes a storage medium operable to store a number of data tracks, a read channel circuit operable to process the data tracks read from the storage medium, and a track quality classifier circuit operable to determine a track quality metric for the data tracks read from the storage medium. The track quality metric indicates whether a corresponding one of the data tracks that has failed to successfully process in the read channel circuit can be reprocessed within a track gap period.

Abstract: An apparatus for processing data includes a storage medium operable to store encoded data, and a read channel circuit with a low density parity check encoder operable to encode data to generate the encoded data, and a low density parity check decoder operable to decode the encoded data retrieved from the storage medium. The read channel circuit is operable to perform a column rotation on the encoded data prior to storage and after retrieval before decoding.

Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.