Patents by Inventor Shaohua Yang

Shaohua Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170123901
    Abstract: Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Zhijun Zhao, Shaohua Yang
  • Publication number: 20170024274
    Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for recovering data where synchronization information is not detected.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 26, 2017
    Inventors: Yuqing Yang, Shaohua Yang, Xuebin Wu, Qi Zuo
  • Publication number: 20170017548
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multiple codeword processing in a data processing system.
    Type: Application
    Filed: July 16, 2015
    Publication date: January 19, 2017
    Inventors: Yang Han, Shaohua Yang, Xuebin Wu
  • Patent number: 9548081
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing to identify a defect on a medium.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 17, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Weijun Tan, Shaohua Yang
  • Patent number: 9542982
    Abstract: An apparatus for processing data includes a data processing circuit configured to process user data, wherein the data processing circuit comprises a number of sub-circuits, a number of clock gates each configured to control a clock signal to one of the sub-circuits, a gating control circuit configured to control the clock gates to apply the clock signal to each of the sub-circuits in staged fashion during a ramped power up operation, and a dummy data source configured to provide dummy data to the data processing circuit during the ramped power up operation of the data processing circuit.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: January 10, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Kaitlyn T. Nguyen, Shaohua Yang, Dan Liu, Xiao Dong Yan, Qi Zuo
  • Patent number: 9536562
    Abstract: A read channel module including an input, a location module and a generation module. The input is configured to receive a read-back signal from a rotating storage medium. The location module is configured to determine a location to insert a first imitation defect within the read-back signal. The first imitation defect imitates a first defect. The generation module is configured to (i) selectively generate the first imitation defect, and (ii) insert the first imitation defect in the read-back signal at the determined location.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: January 3, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Zining Wu, Shaohua Yang
  • Publication number: 20160357633
    Abstract: The present invention is related to systems and methods for storing and recovering data from a distributed storage system.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: Bruce A. Wilson, Shaohua Yang
  • Publication number: 20160314814
    Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Inventors: Yuqing Yang, Shaohua Yang
  • Patent number: 9472237
    Abstract: Embodiments of the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for reducing inter-track interference in relation to processing data retrieved from a storage medium.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 18, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Yuqing Yang, Shaohua Yang
  • Publication number: 20160283321
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for processing data accessed from a flash memory.
    Type: Application
    Filed: March 28, 2015
    Publication date: September 29, 2016
    Inventors: Shaohua Yang, Xuebin Wu, Yang Han
  • Publication number: 20160277035
    Abstract: A non-binary low density parity check decoder includes a check node processor configured to generate check node to variable node messages based on variable node to check node messages, and a variable node processor configured to generate the variable node to check node messages and to calculate perceived values of variable nodes based on the check node to variable node messages. The variable node to check node messages and the check node to variable node messages are in a normalized format. The variable node processor includes an adder configured to add likelihood values in a non-normalized format, wherein only one of two inputs to the adder are converted from the normalized format to the non-normalized format in a zero-padding circuit.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Inventors: Dan Liu, Qi Zuo, Lei Wang, Shaohua Yang
  • Patent number: 9436550
    Abstract: The present invention is related to systems and methods for data storage compression. As an example, a system is discussed that includes a semiconductor device having a host interface, a compression circuit operable to compress a write data set received via the host interface, and a write channel circuit operable to apply an encoding algorithm to the compressed data set to yield an encoded data set.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: September 6, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shaohua Yang, Ebad Ahmed
  • Patent number: 9430270
    Abstract: The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: August 30, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Shaohua Yang
  • Patent number: 9424876
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream. As an example, a data processing system is discussed that includes a sync mark detection circuit and a sync quality output circuit. The sync mark detection circuit is operable to identify a predefined pattern in a received data set, where identification of the predefined pattern results is asserting a sync found output, and where a preamble pattern precedes the predefined pattern in the received data set. The sync quality output circuit is operable to provide a sync mark quality metric indicating a similarity between the preamble pattern and the received data set within a region preceding the predefined pattern.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Shaohua Yang
  • Patent number: 9425823
    Abstract: A data encoder includes an encoding logic circuit configured to encode input data to apply run length limiting using state splitting of a code trellis, and a lookup table configured to apply a block-enumerable map on an un-split version of the code trellis, wherein entries in the lookup table are compressed.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Razmik Karabed, Ebad Ahmed, Victor Krachkovsky, Shaohua Yang, Hakan C. Ozdemir, Zhiwei Wu
  • Publication number: 20160226526
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for error correction in a data processing system.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Yang Han, Shaohua Yang, Xuebin Wu
  • Patent number: 9400797
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. In one particular case, a system is disclosed that includes a stitching circuit and a data recovery circuit. The stitching circuit is operable to: receive a data set including at least a first fragment and a second fragment; replicate data from at least one of the first fragment and the second fragment as stitching values; and aggregate the first fragment with the second fragment with the stitching values between the first fragment and the second fragment to yield a combined data set. The data recovery circuit is operable to process the combined data set to yield an original data set.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: July 26, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shaohua Yang, Xuebin Wu, Shu Li
  • Publication number: 20160210996
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing to identify a defect on a medium.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 21, 2016
    Inventors: Weijun Tan, Shaohua Yang
  • Patent number: 9385756
    Abstract: A data processing system includes a data input configured to receive input blocks of data, a memory configured to store the input blocks of data, a data processor configured to process the input blocks of data and to yield corresponding processed output blocks of data and a scheduler configured to cause the data processor to output the output blocks of data after a processing criterion has been met in the data processor. The memory is configured to retain the input blocks of data for reprocessing after the corresponding processed output blocks of data have been output from the data processor. The scheduler includes a control input configured to receive reprocessing requests for the retained input blocks of data. The scheduler is configured to initiate a reprocessing operation in the data processor for the retained blocks of data when the reprocessing requests are received on the control input.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Johnson Yen, Shaohua Yang, Jefferson E. Singleton, Bruce Wilson, Madhusudan Kalluri
  • Patent number: 9384761
    Abstract: Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for data encoding and decoding.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Shaohua Yang, Yang Han