Patents by Inventor Shaolin Xie

Shaolin Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9146696
    Abstract: A multi-granularity parallel storage system includes an R/W port and a memory. The memory includes W memory blocks and a data gating network. Each of the memory blocks is a 2D array consisting of multiple memory units, and each memory row of the 2D array includes W memory units. For each memory block, one memory row can be read/written at a time, W is the nth power of 2, and n is a natural number.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: September 29, 2015
    Assignee: Institute of Automation, Chinese Academy of Sciences
    Inventors: Donglin Wang, Shaolin Xie, Xiaojun Xue, Zijun Liu, Zhiwei Zhang
  • Publication number: 20140344515
    Abstract: A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.
    Type: Application
    Filed: December 31, 2011
    Publication date: November 20, 2014
    Applicant: Institute of Automation, Chinese Academy of Sciences
    Inventors: Donglin Wang, Zijun Liu, Xiaojun Xue, Xing Zhang, Zhiwei Zhang, Shaolin Xie
  • Publication number: 20140337401
    Abstract: The present disclosure provides A data access method and device for parallel FFT computation. In the method, FFT data and twiddle factors are stored in multi-granularity parallel memories, and divided into groups throughout the computation flow according to a uniform butterfly representation. Each group of data involves multiple butterflies that support parallel computation. Meanwhile, according to the butterfly representation, it is convenient to generate data address and twiddle factor coefficient address for each group. With different R/W granularities, it is possible to read/write data and corresponding twiddle factors in parallel from the multi-granularity memories. The method and device further provide data access devices for parallel FFT computation. In the method and device, no conflict will occur during read/write operations of memories, and no extract step is required for sorting the read/written data.
    Type: Application
    Filed: December 31, 2011
    Publication date: November 13, 2014
    Applicant: Institute of Automation, Chinese Academy of Sciences
    Inventors: Shaolin Xie, Donglin Wang, Xiao Lin, Jie Hao, Xiaojun Xue, Tao Wang, Leizu Yin
  • Publication number: 20140330880
    Abstract: A method and device for multi-granularity parallel FFT butterfly computation. The method and device read data and twiddle factors for computation in one butterfly group from the input buffers and the twiddle factor buffer at a time, perform multi-stage butterfly computation in parallel using uniform butterfly representations, and write the results back to the input buffers. The method and device greatly reduce the frequency for accessing the memory, improve speed for butterfly computation, and reduce power consumption. The method and device achieve multi-granularity butterfly computation of various data formats in a parallel and efficient manner. The method and device can specify the parallel granularity and data format for butterfly computation according to particular applications, and are applicable to FFT butterfly computation of balanced and unbalanced groups.
    Type: Application
    Filed: December 31, 2011
    Publication date: November 6, 2014
    Applicant: Institute of Automation, Chinese Academy of Sciences
    Inventors: Donglin Wang, Tao Wang, Shaolin Xie, Jie Hao, Leizu Yin
  • Publication number: 20140089370
    Abstract: A parallel bit reversal device and method. The device includes a parallel bit reversal unit, a butterfly computation and control unit, and a memory. The butterfly computation and control unit is coupled to the memory via a data bus. The parallel bit reversal unit is configured to bit-reverse butterfly group data used by the butterfly computation and control unit. The parallel bit reversal unit includes an address reversing logic coupled to the butterfly computation and control unit, and configured to perform mirror reversal and right-shift operations on a read address from the butterfly computation and control unit.
    Type: Application
    Filed: December 31, 2011
    Publication date: March 27, 2014
    Applicant: Institute of Automation, Chinese Academy of Sciences
    Inventors: Shaolin Xie, Donglin Wang, Jie Hao, Tao Wang, Leizu Yin
  • Publication number: 20140089369
    Abstract: A multi-granularity parallel FFT computation device including three memories, a butterfly computation device, a state control unit, a data reversing network and a first selector. The three memories are each a multi-granularity parallel memory, and store butterfly group data and twiddle factors corresponding to the butterfly group data. The butterfly computation device perform computations of a butterfly group based on the butterfly group data outputted from the first selector and the corresponding twiddle factors outputted from one of the memories, and write a computation result back to the other two memories. The device can read butterfly group data and corresponding twiddle factors in parallel from the multi-granularity parallel memories with a specific R/W granularity. No memory conflict will occur in the read operation, and no additional process is required for sorting the read/written data.
    Type: Application
    Filed: December 31, 2011
    Publication date: March 27, 2014
    Applicant: Institute of Automation, Chinese Academy of Scienc of Sciences
    Inventors: Donglin Wang, Shaolin Xie, Jie Hao, Xiao Lin, Tao Wang, Leizu Yin
  • Publication number: 20140082282
    Abstract: A multi-granularity parallel storage system and memory that support parallel read/write of rows and columns in multiple granularities. The storage system includes a R/W port and a memory. The memory includes W memory blocks and a data gating network. Each of the memory blocks is a 2D array consisting of multiple memory units and each memory row of the 2D array includes W memory units. For each memory block, one memory row can be read/written at a time, W is the nth power of 2, and n is a natural number. The storage system can support parallel read/write of matrix row and column data of different data types at the same time, and thus essentially eliminate the need for a transposition operation in signal processing and improve efficiency of signal processing.
    Type: Application
    Filed: December 31, 2011
    Publication date: March 20, 2014
    Applicant: Institute of Automation, Chinese Academy of Sciences
    Inventors: Donglin Wang, Shaolin Xie, Xiaojun Xue, Zijun Liu, Zhiwei Zhang