Abstract: Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Abstract: Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough.

Abstract: A metal oxide semiconductor varactor includes an active area doped well that is disposed within a semiconductor substrate and a gate structure including a first portion that extends over the active area doped well and a second portion that extends over the semiconductor substrate outside of the active area doped well. The varactor further includes at least one active area contact structure formed in physical and electrical connection with the active area doped well, in a three-sided contact-landing area of the active area doped well. Still further, the varactor includes a gate contact structure that is formed in physical and electrical contact with the gate structure in the second portion of the gate structure such that the gate contact structure overlies the semiconductor substrate outside of the active area doped well.

Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.

Abstract: Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Abstract: Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.

Abstract: Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer includes a main device region and a perimeter region. The device layer is patterned with active and test patterns. Test patterns include dummy patterns disposed in a test device area. The wafer is processed to form at least one test device disposed in the perimeter region and one or more active devices disposed in the main device region. The test device determines a design window of the one or more active devices. Additional processing is performed to complete forming the device.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.

Abstract: The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Abstract: Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a high voltage capacitor having a first high voltage plate, a second high voltage plate directly overlying the first high voltage plate, and a high voltage dielectric film between the first and second high voltage plates. The integrated circuit also includes a high density capacitor with a first high density plate that is about co-planar with the second high voltage plate, a second high density plate directly overlying the first high density plate, and a thin high density dielectric film positioned between the first and second high density plates.

Abstract: Devices and methods for forming a device are disclosed. The method includes providing a crystalline-on-insulator substrate having a bulk substrate and a surface substrate separated by a buried insulator layer. The surface substrate is defined with a device region. A transistor having a gate is formed in the device region. A first diffusion region is formed adjacent to a first side of the gate and a second diffusion region is formed adjacent to and displaced away from a second side of the gate. At least a first drift isolation region is formed in the surface substrate adjacent to and underlaps the second side of the gate. A drift well is formed in the surface substrate encompassing the first drift isolation region. A device isolation region surrounding the device region is formed in the surface substrate. The device isolation region includes a second depth which is deeper than a first depth of the first drift isolation region.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.

Abstract: Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer.

Abstract: Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

Abstract: A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C1, C2 and C3). The C1 comprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first C1 plate is served by the gate electrode, a second C1 plate is served by the substrate of the capacitor region and a C1 capacitor dielectric is served by the gate dielectric. The C2 includes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels.

Abstract: Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate, where the substrate includes a buried oxide (BOX) layer positioned between a handle layer and a semiconductor layer. An electronic component overlies the buried oxide layer on a semiconductor layer side, and a gate line is electrically connected to the electronic component. A body line is also electrically connected to the electronic component. A first through BOX contact electrically connects the gate line with the handle layer, and a second through BOX contact electrically connects the body line with the handle layer.