Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.

Abstract: A memory device comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The source region and the drain region are over a substrate. The channel region is between the source region and the drain region. The gate dielectric layer is over the channel region. The MTJ stack is over the gate dielectric layer. The MTJ stack comprises a first ferromagnetic layer, a second ferromagnetic layer with a switchable magnetization, and a tunnel barrier layer between the first and second ferromagnetic layers. The metal gate is over the MTJ stack.

Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

Abstract: A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.

Abstract: A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

Abstract: A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer and a reference layer over the pinned layer. The SOT layer is spaced apart from the memory stack. The free layer is over the memory stack and the SOT layer.