Patents by Inventor Shao-Yu Wang
Shao-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953839Abstract: In a method of cleaning a lithography system, during idle mode, a stream of air is directed, through a first opening, into a chamber of a wafer table of an EUV lithography system. One or more particles is extracted by the directed stream of air from surfaces of one or more wafer chucks in the chamber of the wafer table. The stream of air and the extracted one or more particle are drawn, through a second opening, out of the chamber of the wafer table.Type: GrantFiled: December 5, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yu Tu, Shao-Hua Wang, Yen-Hao Liu, Chueh-Chi Kuo, Li-Jui Chen, Heng-Hsin Liu
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Publication number: 20240088901Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: PO CHUN LU, SHAO-YU WANG
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Patent number: 11855647Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po Chun Lu, Shao-Yu Wang
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Publication number: 20230103750Abstract: A method of balancing workloads among processing elements (PEs) in a neural network processor can include receiving first weights and second weights of a neural network. The first and second weights are associated with a first and a second output channel (OC), respectively. A first PE computes a partial sum (PSUM) of an output activation of the first OC based on the non-zero weights in the first weights. A second PE computes a PSUM of an output activation of the second OC based on the non-zero weights in the second weights. A controller can allocate one or more non-zero weights of the first weights to the second PE for computing the PSUM of the output activation of the first OC to balance a workload.Type: ApplicationFiled: October 6, 2021Publication date: April 6, 2023Applicant: MEDIATEK INC.Inventors: Wei-Ting WANG, Jeng-Yun HSU, Shao-Yu WANG, Han-Lin LI
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Publication number: 20230036554Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.Type: ApplicationFiled: October 10, 2022Publication date: February 2, 2023Inventors: Ming-Chieh TSAI, Shao-Yu WANG
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Patent number: 11494545Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.Type: GrantFiled: February 24, 2021Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Chieh Tsai, Shao-Yu Wang
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Publication number: 20220337253Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: PO CHUN LU, SHAO-YU WANG
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Patent number: 11436483Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.Type: GrantFiled: January 14, 2019Date of Patent: September 6, 2022Assignee: MEDIATEK INC.Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
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Publication number: 20220269847Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.Type: ApplicationFiled: February 24, 2021Publication date: August 25, 2022Inventors: Ming-Chieh TSAI, Shao-Yu WANG
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Patent number: 11394388Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: GrantFiled: December 14, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po Chun Lu, Shao-Yu Wang
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Patent number: 11165269Abstract: The disclosure provides an electronic apparatus, a charging method and a non-volatile computer readable recording medium. The electronic apparatus includes a power module and a processor coupled to the power module. The processor is configured to: obtain a charging start time point of the power module; estimate a charging recovery time point according to usage state information; when an electric quantity of the power module is greater than or equal to a first electric quantity, stop the power module from being charged continuously; and at the charging recovery time point, enable the power module to be charged to a second electric quantity, where the second electric quantity is greater than the first electric quantity.Type: GrantFiled: February 14, 2019Date of Patent: November 2, 2021Assignee: ASUSTEK COMPUTER INC.Inventors: Ding-Jun Yin, Shao-Yu Wang
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Publication number: 20210099177Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: PO CHUN LU, SHAO-YU WANG
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Patent number: 10868545Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: GrantFiled: September 20, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po Chun Lu, Shao-Yu Wang
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Publication number: 20200379518Abstract: An electronic device includes a display module, a frame, and a first magnetic element. The frame has a frame body and a first connector, where the frame body forms an accommodation space, and the first connector is disposed on one side of the frame body. The display module is detachably mounted in the frame and has a second connector disposed on one side of the display module. The first connector is disposed at a position corresponding to a position of the second connector. The first magnetic element is disposed in the frame body, and when the display module mounted in the frame is attracted to the accommodation space through a magnetic force of the first magnetic element, the second connector is electrically connected to the first connector.Type: ApplicationFiled: January 15, 2020Publication date: December 3, 2020Applicant: PEGATRON CORPORATIONInventors: YEN-PO CHEN, Shao-Yu Wang
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Publication number: 20200136627Abstract: A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.Type: ApplicationFiled: September 20, 2019Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: PO CHUN LU, SHAO-YU WANG
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Publication number: 20190303757Abstract: A deep learning accelerator (DLA) includes processing elements (PEs) grouped into PE groups to perform convolutional neural network (CNN) computations, by applying multi-dimensional weights on an input activation to produce an output activation. The DLA also includes a dispatcher which dispatches input data in the input activation and non-zero weights in the multi-dimensional weights to the processing elements according to a control mask. The DLA also includes a buffer memory which stores the control mask which specifies positions of zero weights in the multi-dimensional weights. The PE groups generate output data of respective output channels in the output activation, and share a same control mask specifying same positions of the zero weights.Type: ApplicationFiled: December 14, 2018Publication date: October 3, 2019Inventors: Wei-Ting Wang, Han-Lin Li, Chih Chung Cheng, Shao-Yu Wang
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Publication number: 20190267814Abstract: The disclosure provides an electronic apparatus, a charging method and a non-volatile computer readable recording medium. The electronic apparatus includes a power module and a processor coupled to the power module. The processor is configured to: obtain a charging start time point of the power module; estimate a charging recovery time point according to usage state information; when an electric quantity of the power module is greater than or equal to a first electric quantity, stop the power module from being charged continuously; and at the charging recovery time point, enable the power module to be charged to a second electric quantity, where the second electric quantity is greater than the first electric quantity.Type: ApplicationFiled: February 14, 2019Publication date: August 29, 2019Inventors: Ding-Jun YIN, Shao-Yu WANG
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Publication number: 20190242992Abstract: A warning device and a mobile carrier assembly are provided. The mobile carrier assembly includes a mobile carrier and a warning device mounted at the outside of the mobile carrier. The warning device includes an energy harvesting unit, a battery, an object sensor and a warning element. The energy harvesting unit is used to retrieve an energy from an environment and convert the energy into an electrical energy. The battery is electrically connected with the energy harvesting unit for storing the electrical energy. The object sensor is electrically connected with the battery and used to sense whether an object is present in a predetermined range. The warning element is electrically connected with the object sensor and used to issue an alert when the object sensor senses that an object is present in the predetermined range. The alert includes a sound or light.Type: ApplicationFiled: January 17, 2019Publication date: August 8, 2019Applicant: PEGATRON CORPORATIONInventors: Hsiao-Hao Hsu, Shao-Yu Wang
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Publication number: 20190220742Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.Type: ApplicationFiled: January 14, 2019Publication date: July 18, 2019Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
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Publication number: 20180294392Abstract: A composite conducive to heat dissipation of an LED-mounted substrate includes a ceramic layer being of a thermal conductivity of 20˜24 W/mK; a metal layer being of a thermal conductivity of 100˜200 W/mK; and a graphite layer being of an in-plane thermal conductivity of 950 W/mK and a through-plane thermal conductivity of 3 W/mK, wherein the metal layer is disposed between the ceramic layer and the graphite layer. The composite has one side displaying satisfactory insulation characteristics and the other side displaying satisfactory heat transfer characteristics. The composite incurs low material costs and requires a simple manufacturing process.Type: ApplicationFiled: April 6, 2017Publication date: October 11, 2018Inventors: BIING-JYH WENG, SHAO-YU WANG, HSIN-PING CHANG, WEI-HSING TUAN, TSUNG-TE CHOU