Patents by Inventor Sharad Gupta
Sharad Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11933861Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.Type: GrantFiled: July 8, 2022Date of Patent: March 19, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Sharad Gupta
-
Patent number: 11909410Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.Type: GrantFiled: November 7, 2022Date of Patent: February 20, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Sharad Gupta
-
Patent number: 11901919Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.Type: GrantFiled: April 18, 2022Date of Patent: February 13, 2024Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Abhishek Jain, Sharad Gupta
-
Publication number: 20230259158Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.Type: ApplicationFiled: February 7, 2023Publication date: August 17, 2023Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Sharad GUPTA, Anupam JAIN
-
Publication number: 20230061509Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.Type: ApplicationFiled: July 28, 2022Publication date: March 2, 2023Applicant: STMicroelectronics International N.V.Inventors: Sharad GUPTA, Ankur BAL
-
Publication number: 20230054364Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.Type: ApplicationFiled: November 7, 2022Publication date: February 23, 2023Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Sharad GUPTA
-
Publication number: 20230024278Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.Type: ApplicationFiled: July 8, 2022Publication date: January 26, 2023Applicant: STMicroelectronics International N.V.Inventors: Ankur Bal, Sharad Gupta
-
Patent number: 11522553Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.Type: GrantFiled: May 3, 2021Date of Patent: December 6, 2022Assignee: STMicroelectronics International N.V.Inventors: Ankur Bal, Sharad Gupta
-
Publication number: 20220345149Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.Type: ApplicationFiled: April 18, 2022Publication date: October 27, 2022Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Abhishek JAIN, Sharad GUPTA
-
Publication number: 20210351780Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.Type: ApplicationFiled: May 3, 2021Publication date: November 11, 2021Applicant: STMicroelectronics International N.V.Inventors: Ankur BAL, Sharad GUPTA
-
Patent number: 11043271Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.Type: GrantFiled: January 31, 2018Date of Patent: June 22, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Arun Kumar Shukla, Sharad Gupta, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed
-
Patent number: 11037627Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.Type: GrantFiled: January 31, 2018Date of Patent: June 15, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Arun Kumar Shukla, Sharad Gupta, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed
-
Patent number: 10732838Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks.Type: GrantFiled: January 31, 2018Date of Patent: August 4, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Noor Mohamed, Athira Kanchiyil, Sharad Gupta, Arunkumar Mani, Silky Mohanty, Arun Kumar Shukla
-
Patent number: 10560698Abstract: A graphics server and method for streaming rendered content via a remote graphics rendering service is provided. In one embodiment, the server includes a memory, a graphics renderer, a frame capturer, an encoder, and a processor. The memory is configured to store a pre-computed skip-frame message indicative to a client to re-use a previously transmitted frame of the video stream. The graphics renderer is configured to identify when rendered content has not changed. When the graphics renderer identifies that the rendered content has not changed, the processor is configured to cause: (1) the frame capturer to not capture the frames of the rendered content; (2) the encoder to not encode the frames of the rendered content; and (3) the pre-encoded skip-frame message to be transmitted without requiring any pixel processing.Type: GrantFiled: November 6, 2018Date of Patent: February 11, 2020Assignee: Nvidia CorporationInventors: Thomas Meier, Chong Zhang, Bhanu Murthy, Sharad Gupta, Karthik Vijayan
-
Publication number: 20190163369Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a grouping circuit that directs a single level writing circuit to write data corresponding to a first logical group to a set of single level cell blocks of a plurality of single level cell blocks.Type: ApplicationFiled: January 31, 2018Publication date: May 30, 2019Applicant: Western Digital Technologies, Inc.Inventors: Noor Mohamed, Athira Kanchiyil, Sharad Gupta, Arunkumar Mani, Silky Mohanty, Arun Kumar Shukla
-
Publication number: 20190164598Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.Type: ApplicationFiled: January 31, 2018Publication date: May 30, 2019Applicant: Western Digital Technologies, Inc.Inventors: Arun Kumar Shukla, Sharad Gupta, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed
-
Publication number: 20190163386Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.Type: ApplicationFiled: January 31, 2018Publication date: May 30, 2019Applicant: Western Digital Technologies, Inc.Inventors: Arun Kumar Shukla, Sharad Gupta, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed
-
Publication number: 20190075297Abstract: A graphics server and method for streaming rendered content via a remote graphics rendering service is provided. In one embodiment, the server includes a memory, a graphics renderer, a frame capturer, an encoder, and a processor. The memory is configured to store a pre-computed skip-frame message indicative to a client to re-use a previously transmitted frame of the video stream. The graphics renderer is configured to identify when rendered content has not changed. When the graphics renderer identifies that the rendered content has not changed, the processor is configured to cause: (1) the frame capturer to not capture the frames of the rendered content; (2) the encoder to not encode the frames of the rendered content; and (3) the pre-encoded skip-frame message to be transmitted without requiring any pixel processing.Type: ApplicationFiled: November 6, 2018Publication date: March 7, 2019Inventors: Thomas Meier, Chong Zhang, Bhanu Murthy, Sharad Gupta, Karthik Vijayan
-
Patent number: D857192Type: GrantFiled: December 13, 2016Date of Patent: August 20, 2019Assignee: Merck Sharp & Dohme Corp.Inventors: Greg Burkett, Shu Kuen Chang, Angie Kim, Jin Ko, Scott Mackie, Philip G. Green, Sharad Gupta, Angela M. Amend Kwasnik, Christin L. O'Neill, Robert Stianchi, Witold Swiatek
-
Patent number: D870270Type: GrantFiled: July 28, 2017Date of Patent: December 17, 2019Assignee: Merck Sharp & Dohme Corp.Inventors: Greg Burkett, Shu Kuen Chang, Angie Kim, Jin Ko, Scott Mackie, Philip G. Green, Sharad Gupta, Angela M. Amend Kwasnik, Christin L. O'Neill, Robert Stianchi, Witold Swiatek