Patents by Inventor Shashank C. Deshmukh
Shashank C. Deshmukh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9396961Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.Type: GrantFiled: February 2, 2015Date of Patent: July 19, 2016Assignee: Lam Research CorporationInventors: Reza Arghavani, Shashank C. Deshmukh, Eric A. Hudson, Tom Kamp, Samantha Tan, Gerardo Adrian Delgadino
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Publication number: 20160181117Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.Type: ApplicationFiled: February 2, 2015Publication date: June 23, 2016Inventors: Reza Arghavani, Shashank C. Deshmukh, Eric A. Hudson, Tom Kamp, Samantha Tan, Gerardo Adrian Delgadino
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Patent number: 9079228Abstract: A method for cleaning metallic contaminants from an upper electrode used in a plasma chamber. The method comprises a step of soaking the upper electrode in a cleaning solution of concentrated ammonium hydroxide, hydrogen peroxide and water. The cleaning solution is free of hydrofluoric acid and hydrochloric acid. The method further comprises an optional step of soaking the upper electrode in dilute nitric acid and rinsing the cleaned upper electrode.Type: GrantFiled: December 7, 2010Date of Patent: July 14, 2015Assignee: Lam Research CorporationInventors: Hong Shih, Armen Avoyan, Shashank C. Deshmukh, David Carman
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Patent number: 8722547Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.Type: GrantFiled: April 17, 2007Date of Patent: May 13, 2014Assignee: Applied Materials, Inc.Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
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Publication number: 20130344701Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.Type: ApplicationFiled: June 28, 2013Publication date: December 26, 2013Inventors: Wei LIU, Eiichi MATSUSUE, Meihua SHEN, Shashank C. DESHMUKH, Anh-Kiet Quang PHAN, David PALAGASHVILI, Michael D. WILLWERTH, Jong I. SHIN, Barrett FINCH, Yohei KAWASE
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Publication number: 20110146704Abstract: A method for cleaning metallic contaminants from an upper electrode used in a plasma chamber. The method comprises a step of soaking the upper electrode in a cleaning solution of concentrated ammonium hydroxide, hydrogen peroxide and water. The cleaning solution is free of hydrofluoric acid and hydrochloric acid. The method further comprises an optional step of soaking the upper electrode in dilute nitric acid and rinsing the cleaned upper electrode.Type: ApplicationFiled: December 7, 2010Publication date: June 23, 2011Applicant: Lam Research CorporationInventors: Hong Shih, Armen Avoyan, Shashank C. Deshmukh, David Carman
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Patent number: 7771606Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.Type: GrantFiled: February 22, 2007Date of Patent: August 10, 2010Assignee: Applied Materials, Inc.Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
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Patent number: 7754610Abstract: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.Type: GrantFiled: June 2, 2006Date of Patent: July 13, 2010Assignee: Applied Materials, Inc.Inventors: Kyeong-Tae Lee, Jinhan Choi, Bi Jang, Shashank C. Deshmukh, Meihua Shen, Thorsten B. Lill, Jae Bum Yu
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Patent number: 7737042Abstract: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.Type: GrantFiled: February 22, 2007Date of Patent: June 15, 2010Assignee: Applied Materials, Inc.Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
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Patent number: 7718538Abstract: A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.Type: GrantFiled: February 21, 2007Date of Patent: May 18, 2010Assignee: Applied Materials, Inc.Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorov, Shashank C. Deshmukh
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Publication number: 20080206900Abstract: A pulsed plasma system for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. The ON state of a duty cycle is of a duration sufficiently short to substantially inhibit micro-loading in a reaction region adjacent to the sample, while the OFF state of the duty cycle is of a duration sufficiently long to substantially enable removal of a set of etch by-products from the reaction region. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
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Publication number: 20080206901Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.Type: ApplicationFiled: February 22, 2007Publication date: August 28, 2008Inventors: TAE WON KIM, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
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Publication number: 20080197110Abstract: A pulsed plasma system with pulsed sample bias for etching semiconductor structures is described. In one embodiment, a portion of a sample is removed by applying a pulsed plasma process, wherein the pulsed plasma process comprises a plurality of duty cycles. A negative bias is applied to the sample during the ON state of each duty cycle, while a zero bias is applied to the sample during the OFF state of each duty cycle. In another embodiment, a first portion of a sample is removed by applying a continuous plasma process. The continuous plasma process is then terminated and a second portion of the sample is removed by applying a pulsed plasma process.Type: ApplicationFiled: February 21, 2007Publication date: August 21, 2008Inventors: Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorov, Shashank C. Deshmukh
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Publication number: 20070281479Abstract: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 as an example of a silicon and chlorine containing passivating gas may be added for additional selectivity.Type: ApplicationFiled: August 31, 2006Publication date: December 6, 2007Applicant: Applied Materials, Inc.Inventors: Kyeong-Tae Lee, Jinhan Choi, Bi Jang, Shashank C. Deshmukh, Meihua Shen, Thorsten B. Lill, Jae Bum Yu
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Publication number: 20070249182Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.Type: ApplicationFiled: April 17, 2007Publication date: October 25, 2007Applicant: Applied Materials, Inc.Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
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Patent number: 7122125Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.Type: GrantFiled: November 4, 2002Date of Patent: October 17, 2006Assignee: Applied Materials, Inc.Inventors: Shashank C. Deshmukh, Thorsten B. Lill
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Patent number: 6924088Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.Type: GrantFiled: June 18, 2003Date of Patent: August 2, 2005Assignee: Applied Materials, Inc.Inventors: David S. L. Mui, Wei Liu, Shashank C. Deshmukh, Hiroki Sasano
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Publication number: 20040084409Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.Type: ApplicationFiled: November 4, 2002Publication date: May 6, 2004Applicant: Applied Materials, Inc.Inventors: Shashank C. Deshmukh, Thorsten B. Lill
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Publication number: 20040038139Abstract: A method and apparatus for processing a semiconductor wafer is provided for reducing CD microloading variation. OCD metrology is used to inspect a wafer to determine pre-etch CD microloading, by measuring the CD of dense and isolated photoresist lines. Other parameters can also be measured or otherwise determined, such as sidewall profile, photoresist layer thickness, underlying layer thickness, photoresist pattern density, open area, etc. The inspection results are fed forward to the etcher to determine process parameters, such as resist trim time and/or etch conditions, thereby achieving the desired post-etch CD microloading. In certain embodiments, the CD and profile measurements, trim, etch processing and post-etch cleaning are performed at a single module in a controlled environment. All of the transfer and processing steps performed by the module are performed in a clean environment, thereby increasing yield by avoiding exposing the wafer to the atmosphere and possible contamination between steps.Type: ApplicationFiled: June 18, 2003Publication date: February 26, 2004Inventors: David S.L. Mui, Wei Liu, Shashank C. Deshmukh, Hiroki Sasano
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Publication number: 20040018739Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.Type: ApplicationFiled: July 26, 2002Publication date: January 29, 2004Applicant: Applied Materials, Inc.Inventors: Farid Abooameri, Shashank C. Deshmukh, Meihua Shen, Stephanie S. Cheng, Nicolas Gani, Thorsten B. Lill