Abstract: One embodiment of the present invention is an etching method for use in fabricating an integrated circuit device on a wafer or substrate in an inductively coupled plasma reactor in a passivation-driven etch chemistry, which method includes steps of: (a) providing a passivation-driven etch chemistry precursor in a chamber of the reactor wherein a first coil is disposed to supply energy primarily to an outer portion of the chamber and a second coil is disposed to supply energy primarily to an inner portion of the chamber; and (b) providing power to the first coil and the second coil in a ratio of power supplied to the first coil and power supplied to the second coil greater than 1.

Abstract: A method and apparatus for controlling lateral etching during an etching process. The method and apparatus includes laterally etching a lower layer of a stack of layers in a processing chamber, where an endpoint detection system radiates a spectrum of light over the lower layer being etched and an area over the stack of layers proximate to the lower layer being etched. The intensity of light reflected from at least one of the stacked layers positioned lateral to the lower layer being etched is then measured. An endpoint detection system terminates the etching process upon measuring a predetermined metric associated with the intensity of reflected light from the at least one of the stacked layers.

Abstract: An electrostatic chuck 75 for holding a substrate 25 in a process chamber 20, comprises an electrostatic member 80 including an insulator having an electrode 95 therein and a receiving surface for receiving the substrate. A base 85 supports the electrostatic member, the base having a first thermal resistance R.sub.B and having a lower surface that rests on the process chamber. A thermal transfer regulator pad 100 is positioned between the receiving surface of the electrostatic member and the lower surface of the base, the thermal pad comprising a second thermal resistance R.sub.P that is sufficiently higher or lower than the thermal resistance R.sub.B of the base, to provide a predetermined temperature profile across a processing surface of the substrate during processing in the chamber.

Abstract: Apparatus for measuring wafer support pedestal temperature in a semiconductor wafer processing system. The apparatus measures infrared energy emitted by the bottom of the pedestal via a tube having one end inserted in a bore through the underside of the cathode pedestal base. The distal end of the tube is coupled to a temperature sensor. Both the tube and temperature sensor are fitted with insulating sleeve adapters to suppress unwanted RF signals from coupling to the sensor.

Abstract: An etchant composition of nitrogen trifluoride and chlorine, preferably also including a passivation material such as hydrogen bromide, etches tungsten silicide-polysilicon gate layers with high selectivity to a thin underlying silicon oxide gate oxide layer to form straight wall, perpendicular profiles with low microloading and excellent profile control.