Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.

Abstract: One embodiment of the present invention is an etching method for use in fabricating an integrated circuit device on a wafer or substrate in an inductively coupled plasma reactor in a passivation-driven etch chemistry, which method includes steps of: (a) providing a passivation-driven etch chemistry precursor in a chamber of the reactor wherein a first coil is disposed to supply energy primarily to an outer portion of the chamber and a second coil is disposed to supply energy primarily to an inner portion of the chamber; and (b) providing power to the first coil and the second coil in a ratio of power supplied to the first coil and power supplied to the second coil greater than 1.

Abstract: An electrostatic chuck 75 for holding a substrate 25 in a process chamber 20, comprises an electrostatic member 80 including an insulator having an electrode 95 therein and a receiving surface for receiving the substrate. A base 85 supports the electrostatic member, the base having a first thermal resistance R.sub.B and having a lower surface that rests on the process chamber. A thermal transfer regulator pad 100 is positioned between the receiving surface of the electrostatic member and the lower surface of the base, the thermal pad comprising a second thermal resistance R.sub.P that is sufficiently higher or lower than the thermal resistance R.sub.B of the base, to provide a predetermined temperature profile across a processing surface of the substrate during processing in the chamber.

Abstract: Apparatus for measuring wafer support pedestal temperature in a semiconductor wafer processing system. The apparatus measures infrared energy emitted by the bottom of the pedestal via a tube having one end inserted in a bore through the underside of the cathode pedestal base. The distal end of the tube is coupled to a temperature sensor. Both the tube and temperature sensor are fitted with insulating sleeve adapters to suppress unwanted RF signals from coupling to the sensor.

Abstract: An etchant composition of nitrogen trifluoride and chlorine, preferably also including a passivation material such as hydrogen bromide, etches tungsten silicide-polysilicon gate layers with high selectivity to a thin underlying silicon oxide gate oxide layer to form straight wall, perpendicular profiles with low microloading and excellent profile control.