Patents by Inventor Shashank Deshmukh
Shashank Deshmukh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230268192Abstract: A method for selectively etching at least one feature in a first region with respect to a second region of a stack is provided. The first region is selectively etched with respect to the second region to form at least one partial feature in the first region, the at least one partial feature having a depth with respect to a surface of the second region. An in-situ a fluorine-free, non-conformal, carbon-containing mask is deposited over the first region and the second region, wherein the carbon-containing mask is selectively deposited on the second region at a second thickness with respect to the first region at a first thickness, the second thickness being greater than the first thickness. The first region is further etched in-situ to etch the at least one partial feature and wherein the carbon-containing mask acts as an etch mask for the second region.Type: ApplicationFiled: June 13, 2022Publication date: August 24, 2023Inventors: Eric HUDSON, Kapu Sirish REDDY, Ragesh PUTHENKOVILAKAM, Shashank DESHMUKH, Prabhat KUMAR, Prabhakara GOPALADASU, Seokmin YUN, Xin ZHANG
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Patent number: 10361091Abstract: A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.Type: GrantFiled: May 31, 2017Date of Patent: July 23, 2019Assignee: Lam Research CorporationInventors: Eric Hudson, Shashank Deshmukh, Sonny Li, Chia-Chun Wang, Prabhakara Gopaladasu, Zihao Ouyang
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Publication number: 20180350618Abstract: A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Eric HUDSON, Shashank DESHMUKH, Sonny LI, Chia-Chun WANG, Prabhakara GOPALADASU, Zihao OUYANG
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Patent number: 8956500Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.Type: GrantFiled: April 24, 2007Date of Patent: February 17, 2015Assignee: Applied Materials, Inc.Inventors: Stephen Yuen, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
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Patent number: 8501626Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.Type: GrantFiled: June 25, 2008Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Wei Liu, Eiichi Matsusue, Meihua Shen, Shashank Deshmukh, Anh-Kiet Quang Phan, David Palagashvili, Michael D. Willwerth, Jong I. Shin, Barrett Finch, Yohei Kawase
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Patent number: 8133817Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: GrantFiled: November 30, 2008Date of Patent: March 13, 2012Assignee: Applied Materials, Inc.Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Patent number: 7910488Abstract: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.Type: GrantFiled: July 12, 2007Date of Patent: March 22, 2011Assignee: Applied Materials, Inc.Inventors: Nicolas Gani, Meihua Shen, Shashank Deshmukh
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Patent number: 7780862Abstract: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.Type: GrantFiled: March 21, 2006Date of Patent: August 24, 2010Assignee: Applied Materials, Inc.Inventors: Meihua Shen, Xikun Wang, Wei Liu, Yan Du, Shashank Deshmukh
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Publication number: 20090170333Abstract: Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.Type: ApplicationFiled: November 30, 2008Publication date: July 2, 2009Inventors: Hiroki Sasano, Meihua Shen, Radhika Mani, Sunil Srinivasan, Daehee Weon, Nicolas Gani, Shashank Deshmukh, Anisul Khan
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Patent number: 7504338Abstract: Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.Type: GrantFiled: August 9, 2006Date of Patent: March 17, 2009Assignee: Applied Materials, Inc.Inventors: Yan Du, Meihua Shen, Shashank Deshmukh
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Publication number: 20090017633Abstract: Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over the high-k dielectric layer, and a first polysilicon layer formed over the metal layer, the second stack comprising a second polysilicon layer, wherein the first and second stacks are substantially equal in thickness; (b) simultaneously etching a first feature in the first polysilicon layer and a second feature in the second polysilicon layer until the metal layer in the first stack is exposed; (c) simultaneously etching the metal layer and second polysilicon layer to extend the respective first and second features into the first and second stacks; and (d) etching the high-k dielectric layer.Type: ApplicationFiled: July 12, 2007Publication date: January 15, 2009Applicant: APPLIED MATERIALS, INC.Inventors: NICOLAS GANI, Meihua Shen, Shashank Deshmukh
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Publication number: 20090004870Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.Type: ApplicationFiled: June 25, 2008Publication date: January 1, 2009Inventors: Wei Liu, Eiichi Matsusue, Meihua Shen, Shashank Deshmukh, Anh-Kiet Quang Phan, David Palagashvili, Michael D. Willwerth, Jong I. Shin, Barrett Finch, Yohei Kawase
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Publication number: 20080264904Abstract: An inductively-coupled plasma processing chamber has a chamber with a ceiling. A first and second antenna are placed adjacent to the ceiling. The first antenna is concentric to the second antenna. A plasma source power supply is coupled to the first and second antenna. The plasma source power supply generates a first RF power to the first antenna, and a second RF power to the second antenna. A substrate support disposed within the chamber. The size of the first antenna and a distance between the substrate support are such that the etch rate of the substrate on the substrate support is substantially uniform.Type: ApplicationFiled: April 24, 2007Publication date: October 30, 2008Inventors: STEPHEN YUEN, Kyeong-Tae Lee, Valentin Todorow, Tae Won Kim, Anisul Khan, Shashank Deshmukh
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Patent number: 7368392Abstract: A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.Type: GrantFiled: April 23, 2004Date of Patent: May 6, 2008Assignee: Applied Materials, Inc.Inventors: Jinhan Choi, Shashank Deshmukh, Sang Yi, Kyeong-Tae Lee
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Publication number: 20080011423Abstract: In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.Type: ApplicationFiled: July 13, 2007Publication date: January 17, 2008Applicant: Applied Materials, Inc.Inventors: MEIHUA SHEN, Xikun Wang, Wei Liu, Yan Du, Shashank Deshmukh
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Publication number: 20070281477Abstract: A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NF3 and Cl2. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiCl4 may be added for additional selectivity.Type: ApplicationFiled: June 2, 2006Publication date: December 6, 2007Applicant: Applied Materials, Inc.Inventors: Kyeong-Tae Lee, Jinhan Choi, Bi Jang, Shashank Deshmukh, Meihua Shen, Thorsten Lill, Jae Yu
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Publication number: 20070224813Abstract: In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Applicant: Applied Materials, Inc.Inventors: Meihua Shen, Xikun Wang, Wei Liu, Yan Du, Shashank Deshmukh
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Publication number: 20070010099Abstract: Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF4 to CHF3, where the volumetric ratio of CF4 to CHF3 is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.Type: ApplicationFiled: August 9, 2006Publication date: January 11, 2007Inventors: Yan Du, Meihua Shen, Shashank Deshmukh
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Patent number: 6921723Abstract: Conventional methods of semiconductor fabrication and processing typically utilize three gas (e.g., HBr, Cl2 and O2) and four gas (e.g., HBr, Cl2, O2 and CF4) chemistries to perform gate etching in plasma process chambers. However, the silicon to resist selectivity achieved by these chemistries is limited to about 3:1. The present invention concerns a plasma source gas comprising SF6 and one or more fluorine-containing gases selected from C3F6, C4F8, C5F8, CH2F2, CHF3, and C4F6 (e.g., SF6 and C4F8), allowing the use of a two gas etch chemistry that provides enhanced silicon to photoresist selectivity in gate etching processes.Type: GrantFiled: April 23, 2002Date of Patent: July 26, 2005Assignee: Applied Materials, Inc.Inventors: Yung-Hee Yvette Lee, Shashank Deshmukh
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Publication number: 20050070103Abstract: A method and system for endpoint detection during an etch process is disclosed. The endpoint of the etch process is determined using a predetermined metric associated with the direct measurement of the intensity of radiation reflected from the layer being etched at a pre-selected wavelength. By using a direct measurement of the intensity, the layer being etched can have a thickness on the order of the wavelength of the light used for detection. As such, the present invention finds use in etching very thin, high K dielectric materials such as hafnium dioxide, hafnium silicate and the like.Type: ApplicationFiled: September 29, 2003Publication date: March 31, 2005Inventors: Shashank Deshmukh, Michael Grimbergen