Patents by Inventor Shashank S. Ekbote
Shashank S. Ekbote has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10008499Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.Type: GrantFiled: October 3, 2017Date of Patent: June 26, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
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Patent number: 9922971Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: July 7, 2016Date of Patent: March 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Publication number: 20180047728Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.Type: ApplicationFiled: October 3, 2017Publication date: February 15, 2018Inventors: Kwan-Yong LIM, James Walter BLATCHFORD, Shashank S. EKBOTE, Younsung CHOI
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Patent number: 9812452Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.Type: GrantFiled: October 27, 2016Date of Patent: November 7, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
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Publication number: 20170047329Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Inventors: Kwan-Yong LIM, James Walter BLATCHFORD, Shashank S. EKBOTE, Younsung CHOI
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Patent number: 9508601Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.Type: GrantFiled: December 8, 2014Date of Patent: November 29, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
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Publication number: 20160322352Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: July 7, 2016Publication date: November 3, 2016Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Patent number: 9412741Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: October 22, 2015Date of Patent: August 9, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Patent number: 9406769Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: October 5, 2015Date of Patent: August 2, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Publication number: 20160043076Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Publication number: 20160027888Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Shashank S. EKBOTE, Kwan-Yong LIM, Ebenezer ESHUN, Youn Sung CHOI
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Patent number: 9224653Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.Type: GrantFiled: June 1, 2015Date of Patent: December 29, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Ebenezer Eshun, Shashank S. Ekbote
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Patent number: 9202810Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: April 3, 2014Date of Patent: December 1, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Patent number: 9202883Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: June 19, 2015Date of Patent: December 1, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Publication number: 20150287717Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Publication number: 20150287801Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Shashank S. EKBOTE, Kwan-Yong LIM, Ebenezer ESHUN, Youn Sung CHOI
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Publication number: 20150270174Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.Type: ApplicationFiled: June 1, 2015Publication date: September 24, 2015Inventors: Himadri Sekhar PAL, Ebenezer ESHUN, Shashank S. EKBOTE
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Patent number: 9136382Abstract: A method for fabricating a native device is presented. The method includes forming a gate structure over a substrate starting at an outer edge of an inner marker region, where the gate structure extends in a longitudinal direction, and performing MDD implants, where each implant is performed using a different orientation with respect to the gate structure, performing pocket implants, where each implant is performed using a different orientation with respect to the gate structure, and concentrations of the pocket implants vary based upon the orientations. A transistor fabricated as a native device, is presented, which includes an inner marker region, an active outer region which surrounds the inner marker region, a gate structure coupled to the inner marker region, and first and second source/drain implants located within the active outer region and interposed between the first source/drain implant and the second source/drain implant.Type: GrantFiled: August 23, 2013Date of Patent: September 15, 2015Assignee: QUALCOMM IncorporatedInventors: Shashank S. Ekbote, Rongtian Zhang
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Patent number: 9093298Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: August 22, 2013Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Patent number: 9076670Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.Type: GrantFiled: July 16, 2013Date of Patent: July 7, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Ebenezer Eshun, Shashank S. Ekbote