Abstract: A method of forming an integrated circuit includes forming a gate structure over a semiconductor body, and forming a shadowing structure over the semiconductor body laterally spaced from the gate structure, thereby defining an active area in the semiconductor body therebetween. The method further includes performing an angled implant into the gate structure, wherein the shadowing structure substantially blocks dopant from the angled implant from implanting into the active area, and performing a source/drain implant into the gate structure and the active area.

Abstract: A method is disclosed for doping a target area of a semiconductor substrate, such as a source or drain region of a transistor, with an electronically active dopant (such as an N-type dopant used to create active areas in NMOS devices, or a P-type dopant used to create active areas in PMOS devices) having a well-controlled placement profile and strong activation. The method comprises placing a carbon-containing diffusion suppressant in the target area at approximately 50% of the concentration of the dopant, and activating the dopant by an approximately 1,040 degree Celsius thermal anneal. In many cases, a thermal anneal at such a high temperature induces excessive diffusion of the dopant out of the target area, but this relative concentration of carbon produces a heretofore unexpected reduction in dopant diffusion during such a high-temperature thermal anneal.

Abstract: A method of manufacturing a CMOS semiconductor comprising, forming shallow trench isolation regions in a workpiece, depositing a gate oxide layer on top of the workpiece, depositing a polysilicon layer on top of the gate oxide, performing VTN patterning, performing first series of adjusted implantations, performing post implantation cleaning, performing VTP patterning, performing a second series of adjusted implantations, performing the post implantation cleaning, performing a well implant damage anneal; patterning gate, etching gate, and performing back end of line processing.

Abstract: A method of manufacturing an integrated circuit comprising forming gate structures for first, second and third semiconductor device types located on a semiconductor substrate. A dopant block is formed over the second semiconductor device type and first dopants are implanted into unblocked regions of the semiconductor substrate corresponding to the first and third semiconductor device types. The dopant block is removed and a second dopant block is formed over the first semiconductor device type. Second dopants are implanted into unblocked regions of the semiconductor substrate corresponding to the second and third semiconductor device types.

Abstract: The present invention provides a method for manufacturing a semiconductor device, a semiconductor device, and a method for manufacturing an integrated circuit including a semiconductor device. The method for manufacturing the semiconductor device, without limitation, may include providing a gate dielectric layer (413, 423) and a gate electrode layer (418, 428) over a substrate (310), and forming a gate sidewall spacer (610, 630) along one or more sidewalls of the gate dielectric layer (413, 423) and the gate electrode layer (418, 428) using a plasma enhanced chemical vapor deposition process, and forming different hydrogen concentration in NMOS and PMOS sidewall spacers (610, 630) using a local hydrogen treatment (LHT) method.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Abstract: A method of forming an integrated circuit transistor (80), comprising providing a semiconductor region (90) and forming a gate structure (92, 94) in a fixed position relative to the semiconductor region. The gate structure has a first sidewall (94a) and a second sidewall (94b). The method also comprises first, forming a first layer (96) adjacent the first sidewall and the second sidewall, and second, forming a second layer (98) adjacent the first layer. The method also comprises third, forming a third layer (100) adjacent the second layer, and fourth, forming a fourth layer (102) adjacent the third layer. The method also comprises fifth, implanting a first and second source/drain region (106a, 106b) in the semiconductor region and at a first distance laterally with respect to the gate structure, wherein a combined thickness of the first, second, third, and fourth layers determines the first distance.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.