Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Abstract: Various systems are provided for an apparatus. In one example, the apparatus includes an expansion plenum with a plurality of outlets directing flow in a common first direction, and an inlet receiving flow in a second direction angled with respect to the first common direction. The apparatus further includes at least one mating structure operatively coupled to one of the plurality of outlets, the at least one mating structure configured to provide a determined amount of exhaust gas to an exhaust gas treatment system.

Abstract: Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data.

Abstract: An engine exhaust treatment system includes an upstream turbocharger fluidly coupled with an engine and disposed downstream from the engine along a flow path of exhaust gas generated by the engine, a downstream turbocharger fluidly coupled with the upstream turbocharger and disposed downstream from the upstream turbocharger along the flow path, and an after-treatment receptacle fluidly coupled with and disposed between the upstream and downstream turbochargers along the flow path. The after-treatment receptacle is configured to receive a first filter medium that removes at least one of particulates or a gas constituent from the exhaust gas generated by the engine. In an embodiment, the exhaust gas can flow through the upstream turbocharger prior to flowing through the after-treatment receptacle and can flow through the after-treatment receptacle prior to flowing through the downstream turbocharger along the flow path.

Abstract: A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference voltage, and a third reference voltage greater than the first reference voltage. The system includes a read module to perform a first read operation to determine a state of the memory cell based on the first reference voltage, and in response to a first failure to decode data read from the memory cell in the first read operation, perform a second read operation to determine the state based on the second reference voltage and a third read operation to determine the state based on the third reference voltage.

Abstract: In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region.

Abstract: A turbo encoder includes multiple interleaved parallel concatenated recursive systematic convolutional encoders wherein each recursive systematic convolutional encoder is provided with an LUT that simultaneously provides the output bit pattern as well as the next state value corresponding to a defined set of multiple input bits and present state for operating the recursive systematic convolutional encoder. Thus, the approach works with LUTs, which do the job of both puncturing and multiplexing for four input bits at a time. The proposed approach may operate almost four times faster than the conventional approach, which can handle only one input bit at a time.