Patents by Inventor Shau-Lin Shue

Shau-Lin Shue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTERCONNECT STRUCTURE
    Publication number: 20220130756
    Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line and a second metal line surrounded by a first dielectric layer, a dielectric block over a portion of the first dielectric layer between the first metal line and the second metal line, and a second dielectric layer over the dielectric block, the first metal line and the second metal line. A bottom surface of the second dielectric layer is lower than a top surface of the dielectric block. The interconnect structure also includes a first via surrounded by the second dielectric layer and electrically connected to the first metal line.
    Type: Application
    Filed: January 7, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yen HUANG, Shao-Kuan LEE, Cheng-Chin LEE, Hai-Ching CHEN, Shau-Lin SHUE
  • Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
    Patent number: 11309241
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Graphene Barrier Layer
    Publication number: 20220115327
    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Semiconductor device and manufacturing method thereof
    Patent number: 11296026
    Abstract: A semiconductor device includes a first interlayer dielectric (ILD) layer disposed over a substrate, and a first metal wiring pattern formed in the first interlayer dielectric layer and extending in a first direction parallel with the substrate. In a cross section along a second direction which crosses the first direction and is in parallel with the substrate, a top of the first metal wiring pattern is covered by a first two-dimensional material layer.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Han Lee, Shau-Lin Shue
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20220084941
    Abstract: A semiconductor device includes a first conductive feature, a second conductive feature, and a first dielectric layer positioned between the first conductive feature and the second conductive feature. An etch stop layer is over the first dielectric layer. A cap layer is over the first conductive feature, the second conductive feature, and the etch stop layer.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Shao-Kuan LEE, Hai-Ching CHEN, Hsin-Yen HUANG, Shau-Lin SHUE, Cheng-Chin LEE
  • Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices
    Publication number: 20220068701
    Abstract: A method of forming a semiconductor structure includes removing a top portion of a conductive feature disposed in a first dielectric layer and over a semiconductor substrate to form a first recess, depositing a second dielectric layer over the first dielectric layer, where the second dielectric layer includes a first region disposed vertically above the first recess and a second region disposed adjacent the first region, and forming a third dielectric layer over the second dielectric layer. The method further includes subsequently forming openings in the third dielectric layer that extend to expose the second dielectric layer, depositing a conductive material in the openings, and planarizing the conductive material to form conductive features in the first and the second regions, where the planarizing completely removes portions of the third dielectric layer disposed in the second region.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 3, 2022
    Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
  • Selective deposition of barrier layer
    Patent number: 11251073
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO.
    Inventors: Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Graphene-Assisted Low-Resistance Interconnect Structures and Methods of Formation Thereof
    Publication number: 20220020694
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a first conductive feature embedded within a first dielectric layer, a via disposed over the first conductive feature, a second conductive feature disposed over the via, and a graphene layer disposed over at least a portion of the first conductive feature. The via electrically couples the first conductive feature to the second conductive feature.
    Type: Application
    Filed: August 2, 2021
    Publication date: January 20, 2022
    Inventors: Shin-Yi Yang, Yu-Chen Chan, Ming-Han Lee, Hai-Ching Chen, Shau-Lin Shue
  • Interconnect structure and method for forming the same
    Patent number: 11227833
    Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Kuan Lee, Cheng-Chin Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • INTEGRATED CHIP WITH CAVITY STRUCTURE
    Publication number: 20220013403
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Application
    Filed: July 8, 2020
    Publication date: January 13, 2022
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • Interconnect structure and method for forming the same
    Patent number: 11222843
    Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a metal line over a substrate, forming a first dielectric layer surrounding the metal line, selectively forming a dielectric block over the first dielectric layer without forming the dielectric block on the metal line, forming a second dielectric layer over the dielectric block and the metal line, etching the second dielectric layer to form a via hole corresponding to the metal line, and filling the via hole with a conductive material.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue
  • Method with CMP for metal ion prevention
    Patent number: 11211256
    Abstract: The present disclosure provides a method for fabricating a semiconductor structure that includes a first dielectric layer over a semiconductor substrate, and a first cap layer over the first dielectric layer. The method includes forming a first metal feature in the first dielectric layer; performing a first CMP process on the first metal feature using a first rotation rate; and performing a second CMP process on the first metal feature using a second rotation rate slower than the first rotation rate. The second CMP process may be time-based. The second CMP process may stop on the first cap layer. After performing the second CMP process, the method includes removing the first cap layer. The first CMP process may have a first polishing rate to the first metal feature. The second CMP process may have a second polishing rate to the first metal feature lower than the first polishing rate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue
  • PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA
    Publication number: 20210398898
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Graphene barrier layer
    Patent number: 11205618
    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: December 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Metal Capping Layer and Methods Thereof
    Publication number: 20210391209
    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.
    Type: Application
    Filed: July 27, 2021
    Publication date: December 16, 2021
    Inventors: Shao-Kuan LEE, Cheng-Chin LEE, Hsin-Yen HUANG, Hai-Ching CHEN, Shau-Lin SHUE
  • Semiconductor device with conductors embedded in a substrate
    Patent number: 11201106
    Abstract: A structure includes a first substrate having a front side and a back side and a second substrate having a front side and a back side, wherein the back side of the second substrate is attached to the back side of the first substrate. The structure further includes a device layer over the front side of the second substrate; a first conductor going through a semiconductor layer in the second substrate; and a conductive connection that connects the first conductor to a conductive feature in the device layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ping Chen, Ming-Han Lee, Shau-Lin Shue
  • Fully Self-Aligned Interconnect Structure
    Publication number: 20210384074
    Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Hsin-Ping Chen, Shau-Lin Shue, Min Cao
  • HYBRID INTERCONNECT STRUCTURE FOR SELF ALIGNED VIA
    Publication number: 20210375749
    Abstract: An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Graphene Layer for Reduced Contact Resistance
    Publication number: 20210375777
    Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Methods of Forming Interconnect Structures in Semiconductor Fabrication
    Publication number: 20210375756
    Abstract: A method of fabricating a semiconductor interconnect structure includes forming a via in a dielectric layer, depositing a ruthenium-containing conductive layer over a top surface of the via and a top surface of the dielectric layer, and patterning the ruthenium-containing conductive layer to form a conductive line over the top surface of the via, where a thickness of the conductive line is less than a thickness of the via.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Ming-Han Lee, Shau-Lin Shue