Patents by Inventor Shau-Yin Tseng

Shau-Yin Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10909431
    Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 2, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chien-Hung Lin, Yu-Sheng Lee, Yung-Chao Chen, Chih-Wei Hsu
  • Publication number: 20200201782
    Abstract: A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.
    Type: Application
    Filed: May 30, 2019
    Publication date: June 25, 2020
    Applicants: Industrial Technology Research Institute, National Taiwan University
    Inventors: Che-Wei Tsao, Tei-Wei Kuo, Yuan-Hao Chang, Tzu-Chieh Shen, Shau-Yin Tseng
  • Publication number: 20200201189
    Abstract: An exposure apparatus including an optical device set and a substrate carrying platform is provided. The optical device set includes a plurality of light sources, at least one rotating beam deflector and at least one deflector set. The plurality of light sources are configured to emit a plurality of beams. Each deflector set includes a plurality of deflectors. The substrate carrying platform is configured to move an exposed substrate disposed on the substrate carrying platform relative to the optical device set along a relative movement direction. The plurality of beams sequentially travel through the at least one rotating beam deflector and the plurality of deflectors to be projected on the exposed substrate. Trajectories of the plurality of beams projected on the exposed substrate form a plurality of scan lines through rotation of the at least one rotating beam deflector.
    Type: Application
    Filed: May 28, 2019
    Publication date: June 25, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Chien-Hung Lin, Yung-Chao Chen, Chih-Wei Hsu, Yu-Sheng Lee, Shau-Yin Tseng
  • Publication number: 20190197374
    Abstract: A method and a system for digital direct imaging, an image generating method and an electronic device are provided. The method for digital direct imaging includes: obtaining a first image of a first format; converting the first image into a second image of a second format, wherein the second image includes a contour description; generating a correction parameter according to at least one mark on a substrate; correcting the second image according to the contour description and the correction parameter; and performing a rasterization operation on the corrected second image and imaging the second image processed by the rasterization operation on the substrate by an exposure device.
    Type: Application
    Filed: September 4, 2018
    Publication date: June 27, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chien-Hung Lin, Yu-Sheng Lee, Yung-Chao Chen, Chih-Wei Hsu
  • Patent number: 10274833
    Abstract: An exposing method adapted to a maskless photolithography process. The exposing method includes reading an exposure file; obtaining a plurality of coordinate information corresponding to a plurality of patterns contained in the exposure file, according to the exposure file; generating graphical data, according to the plurality of coordinate information; generating scanning data corresponding to each of a plurality of polygon mirrors or each of at least one polygon mirror group, according to the graphical data and a configuration of the polygon mirrors, wherein every two rotation directions of every two adjacent polygon mirrors of the plurality of polygon mirrors are different, or every two rotation directions of every two adjacent polygon mirrors of the at least one polygon mirror group are different.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 30, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ka-Yi Yeh, Chun-Lung Lin, Shau-Yin Tseng
  • Publication number: 20180196355
    Abstract: An exposing method adapted to a maskless photolithography process. The exposing method includes reading an exposure file; obtaining a plurality of coordinate information corresponding to a plurality of patterns contained in the exposure file, according to the exposure file; generating graphical data, according to the plurality of coordinate information; generating scanning data corresponding to each of a plurality of polygon mirrors or each of at least one polygon mirror group, according to the graphical data and a configuration of the polygon mirrors, wherein every two rotation directions of every two adjacent polygon mirrors of the plurality of polygon mirrors are different, or every two rotation directions of every two adjacent polygon mirrors of the at least one polygon mirror group are different.
    Type: Application
    Filed: May 30, 2017
    Publication date: July 12, 2018
    Inventors: Ka-Yi Yeh, Chun-Lung Lin, Shau-Yin Tseng
  • Patent number: 9626733
    Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: April 18, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Hsu-Yao Huang, I-Hsuan Lu, Tai-Hua Lu, Shau-Yin Tseng, Juin-Ming Lu
  • Publication number: 20160148335
    Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.
    Type: Application
    Filed: November 24, 2014
    Publication date: May 26, 2016
    Inventors: Hsu-Yao Huang, I-Hsuan Lu, Tai-Hua Lu, Shau-Yin Tseng, Juin-Ming Lu
  • Patent number: 9305326
    Abstract: An exemplary embodiment describes a method for tile elimination, including: reading in data of a new tile; reading signature values corresponding to the new tile from a signature value repository; generating signature values for the new tile; comparing the read signature values and the generated signature values of the same tile to determine whether the two sets of signature values being identical; when the two sets of signature values being identical, copying the new tile directly from a tile frame buffer without rendering; otherwise, updating the signature value repository with the generated signature values replacing the stored signature values; rendering the tile; and updating the tile frame buffer with the newly rendered tile.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 5, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Ling Hwang, Shau-Yin Tseng, Tai-Hua Lu
  • Publication number: 20150187123
    Abstract: An exemplary embodiment describes a method for tile elimination, including: reading in data of a new tile; reading signature values corresponding to the new tile from a signature value repository; generating signature values for the new tile; comparing the read signature values and the generated signature values of the same tile to determine whether the two sets of signature values being identical; when the two sets of signature values being identical, copying the new tile directly from a tile frame buffer without rendering; otherwise, updating the signature value repository with the generated signature values replacing the stored signature values; rendering the tile; and updating the tile frame buffer with the newly rendered tile.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 2, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Ling HWANG, Shau-Yin TSENG, Tai-Hua LU
  • Publication number: 20130166852
    Abstract: A method for hibernation mechanism and a computer system therefor are provided. The method includes the followings. An initial process of a hibernation mechanism is performed in a computer system, in which a non-swappable memory of a main memory is partitioned into a plurality of non-swappable segments, and each segment corresponds to a status value indicating whether the content of the segment has been changed. During a process of entering a hibernation state, for each non-swappable segment, it is determined whether the segment is to be written to a storage device according to the status value. The segment is written into the storage device when a determination result indicates the segment has been changed, or else the computer does not write the segment to the storage device when the determination result indicates the segment is has not been changed.
    Type: Application
    Filed: May 14, 2012
    Publication date: June 27, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shi-Wu Lo, Shau-Yin Tseng
  • Patent number: 8165198
    Abstract: An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Yi-Hsuan Fan
  • Patent number: 8126058
    Abstract: Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors to reduce power consumption for video decoders.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Chihhao Chang, Jia-Ming Chen
  • Publication number: 20090110316
    Abstract: An apparatus and a method for performing video decoding processes in parallel are provided. The method is adapted for utilizing a first cluster and a second cluster of a processor to perform the video data decoding process in parallel. The method includes performing a VLD process to the video data with the first cluster, so as to obtain a plurality of coefficients and then performing an IZ process, an IQ process, and an IDCT process to the coefficients with the second cluster, so as to obtain a plurality of pixels values of the video data. When the first cluster decodes a coefficient of the video data, the second cluster performs the IZ, IQ, and IDCT processes to a coefficient previously decoded by the second cluster of the video data. Accordingly, a parallel process is realized and the decoding speed is increased.
    Type: Application
    Filed: June 24, 2008
    Publication date: April 30, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Shau-Yin Tseng, Yi-Hsuan Fan
  • Publication number: 20080025409
    Abstract: Disclosed is a power aware method and apparatus of video decoder on a multi-core platform. The power aware apparatus comprises a power management unit, and a processor unit having an entropy decoder and a decoder. The processor unit has at least one voltage and at least one frequency. One processor of the multi-core platform performs the entropy decoding for a frame, collects the entropy decoded information, and computes the decompressing time. Based on the computed decompressing time, the processor sets up the voltage and frequency for other or all processors. This invention of the power aware method and apparatus reduces power consumption for video decoders.
    Type: Application
    Filed: November 2, 2006
    Publication date: January 31, 2008
    Inventors: Shau-Yin Tseng, Chihhao Chang, Jia-Ming Chen
  • Publication number: 20070274392
    Abstract: A pattern-search based method and apparatus for context-adaptive variable length coding/decoding (CAVLC/CAVLD) is provided. The method analyzes the correlation between bit patterns and blocks. Before CAVLD, a step of bit-stream pattern search is conducted. If a pattern is matched in a look-up table, this invention skips the CAVLD procedure and reconstructs a block directly. Before CAVLC, a step of zig-zag ordered coefficients search is conducted. If a sequence of zig-zag ordered coefficients is matched in a look-up table, a corresponding coded bit-stream can be obtained directly. Compared with the standard CAVLD procedures, this invention improves about 10% performance in memory access speed.
    Type: Application
    Filed: July 21, 2006
    Publication date: November 29, 2007
    Inventors: Shau-Yin Tseng, Tienwei Hsieh
  • Patent number: 7236593
    Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M?1*(y+c)), wherein M and M?1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: June 26, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Chung Lu, Shau-Yin Tseng
  • Publication number: 20040125950
    Abstract: The present invention provides a method for protecting public key schemes from timing, power and fault attacks. In general, this is accomplished by implementing critical operations using “branchless” or fixed execution path routines whereby the execution path does not vary in any manner that can reveal new information about the secret key during subsequent operations. More particularly, the present invention provides a modular exponentiation algorithm without any redundant computation so that it can protect the secret key from C safe error attacks. The improved method also provides an algorithm that doesn't have a store operation with non-certain destination so that the secret key is immune from M safe error attacks.
    Type: Application
    Filed: July 8, 2003
    Publication date: July 1, 2004
    Inventors: Sung-Ming Yen, Chih-Chung Lu, Shau-Yin Tseng
  • Publication number: 20030099352
    Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M−1*(y+c)), wherein M and M−1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.
    Type: Application
    Filed: March 29, 2002
    Publication date: May 29, 2003
    Inventors: Chih-Chung Lu, Shau-Yin Tseng
  • Publication number: 20020172355
    Abstract: There is disclosed a high-performance Booth-encoded Montgomery module for performing the computation of A*B*r−1 (mod N). A Booth encoder is provided for receiving two bits of A to perform a Booth encoding process, so as to produce a Booth code. A multiplicand selector is provided for receiving B and the Booth code so as to select a multiplicand. A first carry propagate adder is provided for adding the output of the multiplicand selector and a previous computation result to output. A multiplexer is provided for receiving four inputs 0, N, 2N, and 3N from a lookup table and selecting one of the inputs to output. A second carry propagate adder is provided for adding the outputs of the first carry propagate adder and the multiplexer to output. A shifter is provided for shifting the output from the second carry propagate adder to right by two bits, so as to produce a computation result.
    Type: Application
    Filed: April 4, 2001
    Publication date: November 21, 2002
    Inventors: Chih-Chung Lu, An-Yeu Wu, Shau-Yin Tseng