Abstract: A pattern-search based method and apparatus for context-adaptive variable length coding/decoding (CAVLC/CAVLD) is provided. The method analyzes the correlation between bit patterns and blocks. Before CAVLD, a step of bit-stream pattern search is conducted. If a pattern is matched in a look-up table, this invention skips the CAVLD procedure and reconstructs a block directly. Before CAVLC, a step of zig-zag ordered coefficients search is conducted. If a sequence of zig-zag ordered coefficients is matched in a look-up table, a corresponding coded bit-stream can be obtained directly. Compared with the standard CAVLD procedures, this invention improves about 10% performance in memory access speed.

Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M?1*(y+c)), wherein M and M?1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.

Abstract: The present invention provides a method for protecting public key schemes from timing, power and fault attacks. In general, this is accomplished by implementing critical operations using “branchless” or fixed execution path routines whereby the execution path does not vary in any manner that can reveal new information about the secret key during subsequent operations. More particularly, the present invention provides a modular exponentiation algorithm without any redundant computation so that it can protect the secret key from C safe error attacks. The improved method also provides an algorithm that doesn't have a store operation with non-certain destination so that the secret key is immune from M safe error attacks.

Abstract: An apparatus for encryption and decryption, capable of use in encryption and decryption of advanced encryption standard. Byte substitution operation and inverse byte substitution operation are to be combined. Byte substitution operation can be expressed as y=M*multiplicative_inverse(x)+c while inverse byte substitution operation can be expressed as x=multiplicative_inverse(M−1*(y+c)), wherein M and M−1 are inverse matrix of each other and c is a constant matrix. Since the two equations employ a look-up table, that is, multiplicative_inverse(x), the lookup tables for use in byte substitution and inverse byte substitution operations are to be combined according to the invention so as to lower hardware complexity of the implementation. In addition, main operations of column mixing operation and inverse column mixing operation are to be rearranged to combine the two operations in part, resulting in simplified hardware implementation.

Abstract: There is disclosed a high-performance Booth-encoded Montgomery module for performing the computation of A*B*r−1 (mod N). A Booth encoder is provided for receiving two bits of A to perform a Booth encoding process, so as to produce a Booth code. A multiplicand selector is provided for receiving B and the Booth code so as to select a multiplicand. A first carry propagate adder is provided for adding the output of the multiplicand selector and a previous computation result to output. A multiplexer is provided for receiving four inputs 0, N, 2N, and 3N from a lookup table and selecting one of the inputs to output. A second carry propagate adder is provided for adding the outputs of the first carry propagate adder and the multiplexer to output. A shifter is provided for shifting the output from the second carry propagate adder to right by two bits, so as to produce a computation result.