Patents by Inventor Shaw Hung Ku

Shaw Hung Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104439
    Abstract: A memory device includes a substrate, a stacked structure, a plurality of channel structures, a plurality of memory layers, and a plurality of shallow isolation structures. The substrate has an upper surface. The stacked structure is disposed on an upper surface of the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternatively stacked on the upper surface. The channel structures penetrate portions of the stacked structure and are electrically connected to the substrate. The memory layers surround the corresponding ones of the channel structures. The shallow isolation structures extend from a top surface of the stacked structure toward the substrate, wherein each of the shallow isolation structures includes a substance having a dielectric constant of less than 3.9.
    Type: Application
    Filed: October 4, 2019
    Publication date: April 8, 2021
    Inventors: Shaw-Hung KU, Cheng-Hsien CHENG, Wen-Jer TSAI
  • Publication number: 20210090735
    Abstract: The present invention provides a method fir emergency treatment by artificial intelligence. An artificial neural network is used as the artificial intelligence. Firstly the artificial neural network is trained to make injury classification, inspection list and medical material scheduling correctly. For a patient entering the hospital, the artificial neural network that has been successfully trained is used to accept a plurality of word vectors and various physiological information of the patient to generate an injury classification. The artificial neural network then determines whether the patient has to perform various inspection items respectively with the highest level of the injury classification. The artificial neural network then determines whether the patient needs the various medical materials with the highest level of the injury classification.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Ren Shi SHYU, Lit Min NG, Shaw Hwa HWANG, Yu CHIANG, Bing Chih YAO, Cheng Yu YEH, Chih Hung CHIANG, Kun Ching CHANG, You Shuo CHEN, Yao Hsing CHUNG, Li Te SHEN, Chi Jung HUANG, Shun Chieh CHANG, Ning Yun KU
  • Patent number: 10796753
    Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 6, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Shaw-Hung Ku, Yin-Jen Chen
  • Patent number: 10673813
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsueh Ming Hang, Shaw Hwa Hwang, Cheng Yu Yeh, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Shun Chieh Chang, Chi Jung Huang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Patent number: 10644018
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 5, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Atsuhiro Suzuki
  • Patent number: 10460797
    Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 29, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
  • Publication number: 20190319033
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei LEE, Cheng-Hsien CHENG, Shaw-Hung KU, Atsuhiro SUZUKI
  • Publication number: 20190304556
    Abstract: The method for programming a non-volatile memory includes the following steps. Perform a program and program verify operation for a memory cell in the non-volatile memory, wherein the program and program verify operation includes applying a sequence of incremental step pulses to the memory cell. Perform a post-verifying operation for the memory cell after the memory cell passes the program and program verify operation. Apply a post-programming pulse to the memory cell if the memory cell fails the post-verifying operation, wherein the amplitude of the post-programming pulse is greater than the amplitude of the last pulse in the sequence of incremental step pulses. Perform a read operation to the non-volatile memory to obtain a failed bit count corresponding to the read operation. Adjust a read reference voltage of the read operation to minimize the failed bit count.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Shaw-Hung KU, Ta-Wei LIN, Cheng-Hsien CHENG, Chih-Wei LEE, Wen-Jer TSAI
  • Publication number: 20190238503
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Hsueh Ming HANG, Shaw Hwa HWANG, Cheng Yu YEH, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Shun Chieh CHANG, Chi Jung HUANG, Li Te SHEN, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Patent number: 10340017
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 2, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai
  • Publication number: 20190139615
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Shaw-Hung KU, Yu-Hung HUANG, Cheng-Hsien CHENG, Chih-Wei LEE, Atsuhiro SUZUKI, Wen-Jer TSAI
  • Publication number: 20190080750
    Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
  • Patent number: 9859007
    Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 2, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
  • Patent number: 9620603
    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a p-n junction in a conductive layer. The method may allow for the production of semiconductor memory devices of reduced size.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: April 11, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Shaw-Hung Ku, Chih-Hsiung Lee
  • Publication number: 20170098478
    Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20170077118
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: CHENG-HSIEN CHENG, CHIH-WEI LEE, SHAW-HUNG KU, WEN-PIN LU
  • Patent number: 9589982
    Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 7, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
  • Publication number: 20170025179
    Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 26, 2017
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
  • Patent number: 9548121
    Abstract: Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n?1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 17, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Wei Lee, Shaw-Hung Ku, Cheng-Hsien Cheng
  • Publication number: 20160372202
    Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku