Patents by Inventor Shaw Hung Ku
Shaw Hung Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11361824Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.Type: GrantFiled: February 2, 2021Date of Patent: June 14, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Cheng-Hsien Cheng, Chun-Chang Lu, Wen-Jer Tsai
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Patent number: 11201169Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.Type: GrantFiled: March 31, 2020Date of Patent: December 14, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Hsiung Lee, Shaw-Hung Ku
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Publication number: 20210305273Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Applicant: MACRONIX International Co., Ltd.Inventors: CHIH-HSIUNG LEE, Shaw-Hung Ku
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Patent number: 11062759Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.Type: GrantFiled: April 1, 2020Date of Patent: July 13, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Cheng-Hsien Cheng, Atsuhiro Suzuki, Yu-Hung Huang, Sheng-Kai Chen, Wen-Jer Tsai
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Patent number: 11037632Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.Type: GrantFiled: March 25, 2020Date of Patent: June 15, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Chih-Chieh Cheng, Cheng-Hsien Cheng, Yu-Hung Huang, Atsuhiro Suzuki, Wen-Jer Tsai
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Publication number: 20210104439Abstract: A memory device includes a substrate, a stacked structure, a plurality of channel structures, a plurality of memory layers, and a plurality of shallow isolation structures. The substrate has an upper surface. The stacked structure is disposed on an upper surface of the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternatively stacked on the upper surface. The channel structures penetrate portions of the stacked structure and are electrically connected to the substrate. The memory layers surround the corresponding ones of the channel structures. The shallow isolation structures extend from a top surface of the stacked structure toward the substrate, wherein each of the shallow isolation structures includes a substance having a dielectric constant of less than 3.9.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Shaw-Hung KU, Cheng-Hsien CHENG, Wen-Jer TSAI
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Patent number: 10796753Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour.Type: GrantFiled: October 29, 2019Date of Patent: October 6, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Hung Huang, Cheng-Hsien Cheng, Shaw-Hung Ku, Yin-Jen Chen
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Patent number: 10644018Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.Type: GrantFiled: April 12, 2018Date of Patent: May 5, 2020Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Atsuhiro Suzuki
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Patent number: 10460797Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.Type: GrantFiled: September 8, 2017Date of Patent: October 29, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
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Publication number: 20190319033Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.Type: ApplicationFiled: April 12, 2018Publication date: October 17, 2019Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Wei LEE, Cheng-Hsien CHENG, Shaw-Hung KU, Atsuhiro SUZUKI
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Publication number: 20190304556Abstract: The method for programming a non-volatile memory includes the following steps. Perform a program and program verify operation for a memory cell in the non-volatile memory, wherein the program and program verify operation includes applying a sequence of incremental step pulses to the memory cell. Perform a post-verifying operation for the memory cell after the memory cell passes the program and program verify operation. Apply a post-programming pulse to the memory cell if the memory cell fails the post-verifying operation, wherein the amplitude of the post-programming pulse is greater than the amplitude of the last pulse in the sequence of incremental step pulses. Perform a read operation to the non-volatile memory to obtain a failed bit count corresponding to the read operation. Adjust a read reference voltage of the read operation to minimize the failed bit count.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Inventors: Shaw-Hung KU, Ta-Wei LIN, Cheng-Hsien CHENG, Chih-Wei LEE, Wen-Jer TSAI
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Patent number: 10340017Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.Type: GrantFiled: November 6, 2017Date of Patent: July 2, 2019Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai
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Publication number: 20190139615Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.Type: ApplicationFiled: November 6, 2017Publication date: May 9, 2019Inventors: Shaw-Hung KU, Yu-Hung HUANG, Cheng-Hsien CHENG, Chih-Wei LEE, Atsuhiro SUZUKI, Wen-Jer TSAI
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Publication number: 20190080750Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.Type: ApplicationFiled: September 8, 2017Publication date: March 14, 2019Inventors: Shaw-Hung Ku, Ta-Wei Lin, Cheng-Hsien Cheng, Chih-Wei Lee, Wen-Jer Tsai
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Patent number: 9859007Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.Type: GrantFiled: June 17, 2015Date of Patent: January 2, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
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Patent number: 9620603Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the formation of a p-n junction in a conductive layer. The method may allow for the production of semiconductor memory devices of reduced size.Type: GrantFiled: April 23, 2015Date of Patent: April 11, 2017Assignee: Macronix International Co., Ltd.Inventors: Shaw-Hung Ku, Chih-Hsiung Lee
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Publication number: 20170098478Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20170077118Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: CHENG-HSIEN CHENG, CHIH-WEI LEE, SHAW-HUNG KU, WEN-PIN LU
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Patent number: 9589982Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.Type: GrantFiled: September 15, 2015Date of Patent: March 7, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20170025179Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.Type: ApplicationFiled: July 24, 2015Publication date: January 26, 2017Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku