Patents by Inventor Shawn D. Lyonsmith
Shawn D. Lyonsmith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869178Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: GrantFiled: December 10, 2020Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Publication number: 20230117100Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Darwin A. Clampitt, Shawn D. Lyonsmith, Matthew J. King, Lise M. Clampitt, John Hopkins, Kevin Y. Titus, Indra V. Chary, Martin Jared Barclay, Anilkumar Chandolu, Pavithra Natarajan, Roger W. Lindsay
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Publication number: 20230043786Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.Type: ApplicationFiled: October 14, 2022Publication date: February 9, 2023Inventors: Darwin A. Clampitt, Roger W. Lindsay, Christopher R. Ritchie, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt
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Patent number: 11532638Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.Type: GrantFiled: August 31, 2020Date of Patent: December 20, 2022Assignee: Micron Technology, Inc.Inventors: Darwin A. Clampitt, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt, John Hopkins, Kevin Y. Titus, Indra V. Chary, Martin Jared Barclay, Anilkumar Chandolu, Pavithra Natarajan, Roger W. Lindsay
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Patent number: 11508746Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.Type: GrantFiled: October 25, 2019Date of Patent: November 22, 2022Assignee: Micron Technology, Inc.Inventors: Darwin A. Clampitt, Roger W. Lindsay, Christopher R. Ritchie, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt
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Publication number: 20220068956Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.Type: ApplicationFiled: August 31, 2020Publication date: March 3, 2022Inventors: Darwin A. Clampitt, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt, John Hopkins, Kevin Y. Titus, Indra V. Chary, Martin Jared Barclay, Anilkumar Chandolu, Pavithra Natarajan, Roger W. Lindsay
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Publication number: 20210126007Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.Type: ApplicationFiled: October 25, 2019Publication date: April 29, 2021Inventors: Darwin A. Clampitt, Roger W. Lindsay, Christopher R. Ritchie, Shawn D. Lyonsmith, Matthew J. King, Lisa M. Clampitt
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Publication number: 20210090246Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: ApplicationFiled: December 10, 2020Publication date: March 25, 2021Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Patent number: 10872403Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: GrantFiled: August 10, 2018Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Patent number: 10672500Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: GrantFiled: May 22, 2019Date of Patent: June 2, 2020Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10650891Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: GrantFiled: May 22, 2019Date of Patent: May 12, 2020Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20200051235Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: ApplicationFiled: August 10, 2018Publication date: February 13, 2020Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Publication number: 20190355418Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: ApplicationFiled: May 22, 2019Publication date: November 21, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20190341122Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: ApplicationFiled: May 22, 2019Publication date: November 7, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10403359Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: GrantFiled: March 12, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 10381101Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: GrantFiled: December 20, 2017Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20190189237Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Publication number: 20190189209Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.Type: ApplicationFiled: March 12, 2018Publication date: June 20, 2019Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
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Patent number: 8563435Abstract: Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.Type: GrantFiled: September 13, 2012Date of Patent: October 22, 2013Assignee: Micron Technology, Inc.Inventors: David A. Daycock, Paul A. Morgan, Shawn D. Lyonsmith, Curtis R. Olson
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Publication number: 20130011940Abstract: Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: David A. Daycock, Paul A. Morgan, Shawn D. Lyonsmith, Curtis R. Olson