Patents by Inventor Shawna M. Liff

Shawna M. Liff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716067
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 25, 2017
    Assignee: Intel Corporation
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
  • Patent number: 9711284
    Abstract: A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 18, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Sasikanth Manipatruni, Shawna M. Liff, Vivek K. Singh
  • Publication number: 20170188455
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Inventors: Yoshihiro Tomita, Joshua D. Heppner, Shawna M. Liff, Pramod Malatkar
  • Publication number: 20170178990
    Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Inventors: Sasha Oster, Srikant Nekkanty, Joshua D. Heppner, Adel A. Elsherbini, Yoshihiro Tomita, Debendra Mallik, Shawna M. Liff, Yoko Sekihara
  • Publication number: 20170179070
    Abstract: Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define a chamber. The platform can be located within the chamber and can be proximate a thermocompression chip bonder. The plasma jet can be located proximate the platform. The plasma jet can be movable about the platform. The plasma jet can include a nozzle arranged to direct a plasma gas onto the platform. Also described are other embodiments for thermocompression bonding.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Donglai David Lu, Jimin Yao, Amrita Mallik, George S. Kostiew, Shawna M. Liff
  • Patent number: 9685388
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 20, 2017
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20170170105
    Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Sanka Ganesan, Shawna M. Liff, Yikang Deng, Debendra Mallik
  • Publication number: 20170131469
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 11, 2017
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Publication number: 20170040238
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: October 18, 2016
    Publication date: February 9, 2017
    Applicant: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Patent number: 9530747
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
  • Patent number: 9520378
    Abstract: A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Shawna M. Liff
  • Publication number: 20160360618
    Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.
    Type: Application
    Filed: December 26, 2014
    Publication date: December 8, 2016
    Inventors: Adel A. ELSHERBINI, Aleksandar ALEKSOV, Sasha N. Oster, Shawna M. LIFF
  • Patent number: 9507086
    Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: November 29, 2016
    Inventors: Mauro J. Kobrinsky, Henning Braunisch, Shawna M. Liff, Peter L. Chang, Bruce A. Block, Johanna M. Swan
  • Patent number: 9502368
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Yoshihiro Tomita, Jiro Kubota, Omkar G. Karhade, Shawna M. Liff, Kinya Ichikawa, Nitin A. Deshpande
  • Publication number: 20160322707
    Abstract: A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.
    Type: Application
    Filed: July 11, 2016
    Publication date: November 3, 2016
    Applicant: Intel Corporation
    Inventors: Vijay K. Nair, Chuan Hu, Shawna M. Liff, Larry E. Mosley
  • Patent number: 9461355
    Abstract: A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic nanocomposite material with aligned magnetic domains, a conductor embedded within the nanocomposite material, and contact pads extending through the nanocomposite material to connect to the conductor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Chuan Hu, Shawna M. Liff, Larry E. Mosley
  • Patent number: 9435967
    Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: September 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Henning Braunisch, Shawna M. Liff, Peter L. Chang
  • Patent number: 9391427
    Abstract: Heat management systems for vertical cavity surface emitting laser (VCSEL) chips are provided. Embodiments of the invention provide substrates having a vertical cavity surface emitting laser chip disposed on the substrate surface and electrically interconnected with the substrate, a thermal frame disposed on the substrate surface and proximate to at least three sides of the vertical cavity surface emitting laser chip, and a thermal interface material disposed between the at least three sides of the vertical cavity surface emitting laser chip and the thermal frame. The substrate can also include a transceiver chip that is operably coupled to a further integrated circuit chip and that is capable of driving the VCSEL chip.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 12, 2016
    Assignee: INTEL CORPORATION
    Inventors: Feras Eid, Shawna M. Liff, Henning Braunisch
  • Publication number: 20160172323
    Abstract: A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: YOSHIHIRO TOMITA, JIRO KUBOTA, OMKAR G. KARHADE, SHAWNA M. LIFF, KINYA ICHIKAWA, NITIN A. DESHPANDE
  • Publication number: 20160155705
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 22, 2016
    Publication date: June 2, 2016
    Inventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff