Patents by Inventor Shawna M. Liff

Shawna M. Liff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thermal management of molded packages
    Patent number: 10424559
    Abstract: An embodiment includes an apparatus comprising: a semiconductor die; package molding that is molded onto and conformal with a first die surface of the semiconductor die and at least two sidewalls of the semiconductor die, the package molding including: (a)(i) a first surface contacting the semiconductor die, (a)(ii) a second surface opposite the first surface, and (a)(iii) an aperture that extends from the first surface to the second surface; and a polymer substantially filling the aperture; wherein the package molding includes a first thermal conductivity (watts per meter kelvin (W/(m·K)) and the polymer includes a second thermal conductivity that is greater than the first thermal conductivity. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Nader N. Abazarnia, Johanna M. Swan, Taesha D. Beasley, Sasha N. Oster, Tannaz Harirchian, Shawna M. Liff
  • Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate
    Patent number: 10418329
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • FLEXIBLE PACKAGING FOR A WEARABLE ELECTRONIC DEVICE
    Publication number: 20190281717
    Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.
    Type: Application
    Filed: September 28, 2016
    Publication date: September 12, 2019
    Inventors: Aleksandar Aleksov, Son V. Nguyen, Rajat Goyal, David B. Lampner, Dilan Seneviratne, Albert S. Lopez, Joshua D. Heppner, Srinivas V. Pietambaram, Shawna M. Liff, Nadine L. Dabby
  • SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS
    Publication number: 20190259705
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: August 22, 2019
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • PIEZOELECTRIC DEVICES FABRICATED IN PACKAGING BUILD-UP LAYERS
    Publication number: 20190252597
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Feras EID, Shawna M. LIFF
  • Quantum computing assemblies
    Patent number: 10380496
    Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Javier A. Falcon, Hubert C. George, Shawna M. Liff, James S. Clarke
  • Assembly architecture employing organic support for compact and improved assembly throughput
    Patent number: 10368439
    Abstract: An apparatus including a substrate including a first side and an opposite second side; at least one first circuit device on the first side of the substrate, at least one second device on the second side of the substrate; and a support on the second side of the substrate, the support including interconnections connected to the at least one first and second circuit device, the support having a thickness dimension operable to define a dimension from the substrate greater than a thickness dimension of the at least one second circuit device. A method including disposing at least one first circuit component on a first side of a substrate; disposing at least one second circuit component on a second side of the substrate; and coupling a support to the substrate, the substrate defining a dimension from the substrate greater than a thickness dimension of the at least one second circuit component.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: July 30, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Aleksandar Aleksov, Sasha N. Oster, Shawna M. Liff
  • SEMICONDUCTOR PACKAGE HAVING INTEGRATED STIFFENER REGION
    Publication number: 20190214338
    Abstract: Semiconductor packages that mitigate warpage and/or other types or mechanical deformation of package substrates are provided. In some embodiments, a package substrate can include a peripheral conductive region having an assembly of rigid conductive members, such as metal layers, metal interconnects, or a combination thereof. The peripheral conductive region can be integrated into the package substrate during the manufacturing of the package substrate. In some implementations, lithographically defined conductive members can be leveraged to form extended conductive layers that can provide increased stiffness compared to nearly cylindrical conductive vias. Non-peripheral conductive regions also can be integrated into a semiconductor package in order to reduce specific patterns of mechanical deformations and/or to provide other functionality, such as electromagnetic interference (EMI) shielding.
    Type: Application
    Filed: September 14, 2016
    Publication date: July 11, 2019
    Inventors: Eng Huat GOH, Jiun Hann SIR, Min Suet LIM, Shawna M. LIFF, Feras EID
  • STACKED DIE ARCHITECTURES WITH IMPROVED THERMAL MANAGEMENT
    Publication number: 20190214328
    Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Feras Eid, Shrenik Kothari, Chandra M. Jha, Johanna M. Swan, Michael J. Baker, Shawna M. Liff, Thomas L. Sounart, Betsegaw K. Gebrehiwot, Shankar Devasenathipathy, Taylor Gaines, Digvijay Ashokkumar Raorane
  • CO-EXTRUSION OF MULTI-MATERIAL SETS FOR MILLIMETER-WAVE WAVEGUIDE FABRICATION
    Publication number: 20190207290
    Abstract: A method of making a waveguide, comprises: extruding a first dielectric material as a waveguide core of the waveguide, wherein the waveguide core is elongate; and coextruding an outer layer with the waveguide core, wherein the outer layer is arranged around the waveguide core.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 4, 2019
    Inventors: Brandon M. Rawlings, Shawna M. Liff, Sasha N. Oster, Georgios C. Dogiamis, Telesphor Kamgaing, Adel A. Elsherbini, Aleksandar Aleksov, I, Johanna M. Swan, Richard J. Dischier
  • STRESS ISOLATION FOR SILICON PHOTONIC APPLICATIONS
    Publication number: 20190206782
    Abstract: Techniques of minimizing or eliminating stresses in silicon photonic integrated circuits (Si-PICs) and in semiconductor packages having one or more Si-PICs (Si-PIC packages) are described. An Si-PIC or an Si-PIC package includes a stress minimization solution that assists with filtering out stresses by selectively isolating photonic and/or electronic devices, by isolating components or devices in an Si-PIC or an Si-PIC package that are sources of stress, or by isolating an Si-PIC in an Si-PIC package. The stress minimization solution may include strategically placed cavities and a stage that assist with minimizing or preventing transfer of stress to one or more photonic and/or electronic devices in an Si-PIC or an Si-PIC package.
    Type: Application
    Filed: December 30, 2017
    Publication date: July 4, 2019
    Inventors: Siddarth KUMAR, Shawna M. LIFF
  • METHODS FOR CONDUCTIVELY COATING MILLIMETER WAVEGUIDES
    Publication number: 20190198961
    Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Inventors: Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • WAVEGUIDE TOPOLOGIES FOR RACK SCALE ARCHITECTURE SERVERS
    Publication number: 20190198965
    Abstract: An apparatus comprises a waveguide section including an outer layer of conductive material tubular in shape and having multiple ends; and a joining feature on at least one of the ends of the waveguide section configured for joining to a second separate waveguide section.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 27, 2019
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Sasha N. Oster, Adel A. Elsherbini, Brandon M. Rawlings, Aleksandar Aleksov, Shawna M. Liff, Richard J. Dischler, Johanna M. Swan
  • ROBUST MOLD INTEGRATED SUBSTRATE
    Publication number: 20190189567
    Abstract: An apparatus, comprising an Integrated Circuit (IC) package comprising a dielectric, the IC package has a first surface and an opposing second-surface, wherein the first surface is separated from the second surface by a thickness of the IC package, wherein sidewalls extend along a perimeter and through the thickness between the first surface and the second surface, and a structure comprising a frame that extends at least partially along the perimeter of the IC package, wherein the structure extends at least through the thickness of the IC package and inwardly from the sidewalls of the IC package.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventors: Jimin Yao, Kyle Yazzie, Shawna M. Liff
  • Shielded interconnects
    Patent number: 10319896
    Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Javier A. Falcon, Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Ye Seul Nam, James S. Clarke, Jeanette M. Roberts, Roman Caudillo
  • MILLIMETER-WAVE HOLEY WAVEGUIDES AND MULTI-MATERIAL WAVEGUIDES
    Publication number: 20190173149
    Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 6, 2019
    Inventors: Adel A. Elsherbini, Sasha N. Oster, Georgios C. Dogiamis, Telesphor Kamgaing, Shawna M. Liff, Aleksandar Aleksov, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • PIEZOELECTRIC PACKAGE-INTEGRATED PRESSURE SENSING DEVICES
    Publication number: 20190165250
    Abstract: Embodiments of the invention include a pressure sensing device having a membrane that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material positioned in proximity to the membrane, and an electrode in contact with the piezoelectric material. The membrane deflects in response to a change in ambient pressure and this deflection causes a voltage to be generated in the piezoelectric material with this voltage being proportional to the change in ambient pressure.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 30, 2019
    Inventors: Thomas L. SOUNART, Feras EID, Sasha N. OSTER, Georgios C. DOGIAMIS, Adel A. ELSHERBINI, Shawna M. LIFF, Johanna M. SWAN
  • Piezoelectric devices fabricated in packaging build-up layers
    Patent number: 10305019
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Feras Eid, Shawna M. Liff
  • Thermocompression bonding using plasma gas
    Patent number: 10297567
    Abstract: Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define a chamber. The platform can be located within the chamber and can be proximate a thermocompression chip bonder. The plasma jet can be located proximate the platform. The plasma jet can be movable about the platform. The plasma jet can include a nozzle arranged to direct a plasma gas onto the platform. Also described are other embodiments for thermocompression bonding.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Donglai David Lu, Jimin Yao, Amrita Mallik, George S. Kostiew, Shawna M. Liff
  • PIEZOELECTRIC DEVICES FABRICATED IN PACKAGING BUILD-UP LAYERS
    Publication number: 20190140158
    Abstract: Piezoelectric devices are described fabricated in packaging buildup layers. In one example, a package has a plurality of conductive routing layers and a plurality of organic dielectric layers between the conductive routing layers. A die attach area has a plurality of vias to connect to a microelectronic die, the vias connecting to respective conductive routing layers. A piezoelectric device is formed on an organic dielectric layer, the piezoelectric device having at least one electrode coupled to a conductive routing layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: May 9, 2019
    Inventors: Feras Eid, Shawna M. Liff