Patents by Inventor Shay Gueron

Shay Gueron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9641320
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9641319
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634828
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634830
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634829
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • METHOD, APPARATUS, AND INSTRUCTIONS FOR SAFELY STORING SECRETS IN SYSTEM MEMORY
    Publication number: 20170103026
    Abstract: Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor includes a hardware key, an instruction unit, and an encryption unit. The instruction unit is to receive an encryption instruction and a compare instruction. The encryption instruction is to have a first plaintext input value. The compare instruction is to have a second plaintext input value. The encryption unit is to, in response to the encryption instruction, encrypt the first plaintext input value using the hardware key to generate a ciphertext value, and, in response to the compare instruction, decrypt the ciphertext value using the hardware key to generate a plaintext output value and compare the plaintext output value to the second plaintext input value.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Inventor: Shay Gueron
  • SM4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    Publication number: 20170085370
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Applicant: lntel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • Method, apparatus, and instructions for safely storing secrets in system memory
    Patent number: 9559848
    Abstract: Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor includes a hardware key, an instruction unit, and an encryption unit. The instruction unit is to receive an encryption instruction and a compare instruction. The encryption instruction is to have a first plaintext input value. The compare instruction is to have a second plaintext input value. The encryption unit is to, in response to the encryption instruction, encrypt the first plaintext input value using the hardware key to generate a ciphertext value, and, in response to the compare instruction, decrypt the ciphertext value using the hardware key to generate a plaintext output value and compare the plaintext output value to the second plaintext input value.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: January 31, 2017
    Assignee: INTEL CORPORATION
    Inventor: Shay Gueron
  • On-the-fly key generation for encryption and decryption
    Patent number: 9544133
    Abstract: Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: Sanu K. Mathew, Farhana Sheikh, Ram K. Krishnamurthy, Michael E. Kounavis, Shay Gueron
  • Obscuring memory access patterns in conjunction with deadlock detection or avoidance
    Patent number: 9524240
    Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Gad Sheaffer, Shlomo Raikin
  • SM4 acceleration processors, methods, systems, and instructions
    Patent number: 9513913
    Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values. The processor also includes an execution unit coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • Performing AES Encryption Or Decryption In Multiple Modes With A Single Instruction
    Publication number: 20160261406
    Abstract: A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 8, 2016
    Inventors: Martin Dixon, Srinivas Chennupaty, Shay Gueron
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160248580
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: August 25, 2016
    Applicant: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • VECTOR OPERATIONS WITH OPERAND BASE SYSTEM CONVERSION AND RE-CONVERSION
    Publication number: 20160239300
    Abstract: Methods and apparatuses relating to vector operations with operand base system conversion and re-conversion are described. In one embodiment, a method includes executing a single instruction by receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system, converting the vector elements into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector, performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result, accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system, and converting contents of the register into the first base system.
    Type: Application
    Filed: April 28, 2016
    Publication date: August 18, 2016
    Inventors: Shay Gueron, Vlad Krasnov
  • SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    Publication number: 20160232382
    Abstract: A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
    Type: Application
    Filed: April 18, 2016
    Publication date: August 11, 2016
    Applicant: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD
    Publication number: 20160204938
    Abstract: Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256).
    Type: Application
    Filed: October 12, 2015
    Publication date: July 14, 2016
    Inventors: Michael E. Kounavis, Shay Gueron, Ram Krishnamurthy, Sanu K. Mathew
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160197720
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: October 1, 2015
    Publication date: July 7, 2016
    Applicant: Intel Corporation
    Inventors: SHAY GUERON, WAJDI K FEGHALI, VINODH GOPAL, RAGHUNANDAN MAKARAM, MARTIN G DIXON, SRINIVAS CHENNUPATY, MICHAEL KOUNAVIS
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160196219
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: October 1, 2015
    Publication date: July 7, 2016
    Applicant: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael Kounavis
  • Number squaring computer-implemented method and apparatus
    Patent number: 9383966
    Abstract: Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A computer-implemented method to square a number x may include storing a t-digit vector representation of x in t b-bit registers of a processor. A 2t-digit intermediate vector may be generated and stored in 2t b-bit registers of the processor, using x stored in said t b-bit registers. A value stored in at least one of the t b-bit or 2t b-bit registers may be shifted to the left by n. n may be an integer at least equal to 1. At some point after the shifting, w, square of the number x, may be represented by the 2t-digit result vector stored in the 2t b-bit registers. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Vlad Krasnov
  • METHOD AND APPARATUS FOR PERFORMING BIG-INTEGER ARITHMETIC OPERATIONS
    Publication number: 20160179470
    Abstract: An apparatus and method are described for performing big integer arithmetic operations. For example, one embodiment of a processor comprises: a first source register to store a first 256-bit integer operand; a second source register to store a second 256-bit integer operand; and multiplication logic comprising a set of multipliers and adders to perform a multiplication of the first and second 256-bit integer operands to generate a 512-bit result responsive to a 256-bit multiplication instruction, the multiplication logic to convert a radix representation of the first and second 256-bit integer operands from a first radix representation to a second radix representation selected based on a size of the multipliers and adders used to perform the multiplication and generate a result, and then to convert the result back to the first radix representation.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Shay Gueron, Vlad Krasnov