Abstract: A method and apparatus for efficient power amplification of a wideband signal with a correspondingly wide modulation bandwidth includes an envelope detector (220), a soft switch modulator (270), and a power amplifier (260). The soft switch modulator (270) drives a high side switch (330), and a low side switch (340) to amplify a pulsewidth modulated signal. Electrical signal path lengths within a soft switch driver (320) are dynamically modified so as to always turn off one switch before turning on the other.

Abstract: A system and method of using a computer processor (34) to generate a solution to a linear system of equations is provided. The computer processor (34) executes a Jacobi iterative technique to produce outputs representing the solution. Multiplication operations required by the iterative technique are performed using logarithmic arithmetic. With logarithmic arithmetic, a multiplication operation is accomplished using addition. For a given n.times.n matrix A, the computer processor (34) can compute an inverse matrix A.sup.-1 by repeatedly executing the iterative technique to solve n linear systems.

Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Abstract: An electronic apparatus that includes a digital processor (12), a first digital pulse width modulator (304), a second digital pulse width modulator (306), a combining circuit (308), and a load (310). The digital processor (12) produces a first digital signal (314) and a second digital signal (316). The first digital pulse width modulator (304) is responsive to the first digital signal (314), and the second digital pulse width modulator (306) is responsive to the second digital signal (316). The combining circuit (308) is responsive to the first digital pulse width modulator (304) and the second digital pulse width modulator (306). The load (310) is responsive to the combining circuit (308).

Abstract: A method and system for an L.sub.1 norm operation are provided. A sequence of input signals is distributed through a data pipeline to a programmable accumulator. The accumulator sums the input signals to generate an output signal. The L.sub.1 norm operation can be performed using the distance between two vectors.

Abstract: An apparatus that includes a logarithm based processor (216) having at least one digital logarithm converter (202) and a power amplifier (208) responsive to the logarithm based processor (216).

Abstract: A method and system for an L.sub.2 norm operation are provided. A sequence of input signals is converted to a sequence of log signals. The sequence of log signals is distributed through a data pipeline to a plurality of processing elements which effectively multiply each log signal by a factor of two to produce a plurality of term signals. The term signals are then converted to inverse-log signals which are summed to produce a feedback signal. The square-root of the feedback signal is computed to generate an output signal. The log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial. The L.sub.2 norm operation can be performed using the distance between two vectors.

Abstract: An apparatus for amplifying a signal that includes a digital processor (12) producing a first digital signal (20) and a second digital signal (22), a pulse width modulator (32) receiving the first digital signal (20) and producing a pulse width modulated signal, an amplitude restoration module (37) responsive to the pulse width modulator (32), the amplitude restoration module (37) producing an amplitude envelope signal, a frequency upconverter (16) receiving the second digital signal (22) and producing a frequency modulated signal, and a power amplifier (18) responsive to the frequency upconverter and the amplitude restoration module (37). The power amplifier receives the frequency modulated signal and the amplitude envelope signal and produces an amplified output signal.

Abstract: A digital beam forming system includes an array of computing units (60-76) for weighting incoming signals and a plurality of summing processors (80-84) for generating output signals that represent weighted sums corresponding to rows within the array. The digital beam forming system can be incorporated in either a transmitter or receiver used in a radio frequency communications system.

Abstract: In a video processing system (14), a method of detecting and compensating for motion of an image which includes the steps of: detecting a first pixel value, a second pixel value, and a third pixel value, the first pixel value of a first scan line in a first field, the second pixel value of a second scan line in the first field, and the third pixel value in a second field; providing a motion indicator based on the first, second, and third pixel values; selecting a plurality of interpolation coefficients from a memory based on the motion indicator signal; and providing an interpolated color space pixel based on a first color space pixel associated with the first pixel value, a second color space pixel associated with the second pixel value, and based on the plurality of interpolation coefficients.

Abstract: A method and system of identifying text in a handwriting input is provided. The system includes a feature extractor (30) and a classifier (32). The feature extractor (30) extracts a plurality of features from handwriting input. The classifier (32) classifies the handwriting input according to a discriminant function that is based on a polynomial expansion. The text is identified according to the discriminant function output.

Abstract: A video signal is converted into a coefficient signal for each frame in a video image. Each coefficient signal comprises block coefficient signals which represent the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal for only selected frames is transmitted to a receiving computer (130). The coefficient signals are selected based on a number of coefficients in the coefficient signal for a current frame that vary from corresponding coefficients in the coefficient signal for a sequentially previous frame.

Abstract: A method and system for identifying boundaries of characters in handwritten text by classifying segment strokes provides improved performance in a handwriting recognition system. A segment stroke is a portion of handwritten text which includes a boundary between two characters. The segment stroke is recognized by the same method used to recognized characters. Recognition of a segment stroke is accomplished by training a learning machine to act as a classifier which implements a discriminant function based on a polynomial expansion.

Abstract: A cascade tuning controller and a method for use therefor is provided. The control inputs and the control coefficients are multiplied by scaling values. The scaling values are first tuned and the control coefficients are then tuned using a descent-based optimization method in order to optimize system performance.

Abstract: In a method and system for storing a plurality of data blocks in a memory device, blocks of data elements are stored in a two-dimensional address space such that blocks overlap in the address space. The data elements may be digital words which represent exponents of a polynomial expansion. An overlapping data block is segmented into sub-blocks which are separated by null regions. Common data elements that are shared among the blocks are non-redundantly stored in the memory device.

Abstract: An LNS-based computer processor is provided for performing high-speed calculations that involve special function values. Special functions include transcendental and hyperbolic functions. The computer processor includes a decoder (11), a memory circuit (12) for storing a plurality of special function signals, a log converter (14), at least one processing element (16), and an inverse-log converter (18).

Abstract: A pixel map signal is converted into a coefficient signal of block coefficient signals, each representing the pixels in a pixel map block (420) in a pixel map (410) with the coefficients in a hybrid polynomial. The coefficient signal is quantized by dividing each of the coefficient values in each of the block coefficient signals by quantization factors to produce quantized coefficient values which replace the coefficient values. Block coefficient signals which represent an edge block (424) in the pixel map (410) are divided by larger quantization factors than block coefficient signals which represent a center block (422) in the pixel map (410). As a result, smaller quantized coefficient values are obtained so that block coefficient signals which represent an edge block (424) are compressed to a greater extent than block coefficient signals that represent a center block (422) in the pixel map (410).

Abstract: Disclosed is a method for generating a high-resolution, real-time, digital video signal from an analog composite video signal such as an NTSC, PAL, or SECAM signal. The analog video signal is digitized and consecutive fields in the signal are merged to produce a frame. Non-uniform interpolation is performed between adjacent scan lines in the frame to generate the high-resolution video signal.

Abstract: A video signal is converted into a coefficient signal of block coefficient signals for each frame in a video image. Each of the block coefficient signals represents the pixels in a pixel map block (420) with the coefficients in a hybrid polynomial. The hybrid polynomial contains discrete cosine terms, a constant term separated from the discrete cosine terms, and polynomial terms separated from the discrete cosine terms. Coefficient signals for selected frames only are transmitted to a receiving computer (130). The coefficient signals for the selected frames are converted to decompressed pixel map signals and the pixel map signals for unselected frames are interpolated using nonlinear interpolation. The decompressed pixel map signals and interpolated pixel map signals are ordered into an original frame sequence to produce a decompressed video signal.

Abstract: The invention provides a computer-implementable method for detecting substroke boundaries in handwriting input. The method selects pen tip velocity extremas to represent. substroke boundaries. The method includes steps for generating a velocity profile from the handwriting input; identifying a plurality of peak extrema within the velocity profile; identifying a plurality of in-line extrema within the velocity profile; and detecting the substroke boundaries by filtering the plurality of peak extrema and the plurality of in-line extrema.