Abstract: A system for controlling the movement of at least one limb of a person's body includes an interface unit in communication with the person's body for receiving an input signal. A polynomial processor generates a control signal as a polynomial function of the at least one input signal. A generator generates a functional electrical stimulation signal. A plurality of electrodes stimulates the movement of the at least one limb by introducing the functional electrical stimulation signal to the at least one of a plurality of inactive muscles.

Abstract: A pixel map signal is converted into a coefficient signal of block coefficient signals, each representing the pixels in a pixel map block (420) with the coefficients in a hybrid polynomial. The hybrid polynomial contains discrete cosine terms, a constant term separated from the discrete cosine terms, and polynomial terms. Each block coefficient signal contains a background component representing a coefficient of the constant term, a linear component representing the coefficients of a the polynomial terms, and a nonlinear component representing the coefficients of the discrete cosine terms. The background component represents constant, unchanging pixel values in a pixel map block (420), the linear component represents linearly changing pixel values in a pixel map block (420), and the nonlinear component represents nonlinear patterns in a pixel map block (420).

Abstract: A real-time video system which performs non-uniform interpolation between adjacent vertical scan lines is presented. The video system includes a converter, a memory, an enhanced-video circuit, and a sync generator. The video system decodes and digitizes an analog composite video signal, such as an NTSC, PAL, or SECAM signal, and generates a digital video signal having a greater number of horizontal scan lines than the analog video signal. The video system is programmable to allow a different number of scan lines in the output digital video signal.

Abstract: A system for recognizing spoken sounds from continuous speech includes a plurality of classifiers and a selector. Each of the classifiers implements a discriminant function which is based on a polynomial expansion. By determining the polynomial coefficients of a discriminant function, the corresponding classifier is tuned to classify a specific spoken sound. The selector utilizes the classifier outputs to identify the spoken sounds. A method of using the system is also provided.

Abstract: A pixel map signal is separated into block signals, each representing pixels in a pixel map block (420) in a pixel map (410). The blocks signals each contain an overlap component having pixel values representing pixels contained both by the corresponding pixel map block (420) and an adjacent block. The pixel map signal is compressed by converting the block signals into a coefficient signal of block coefficient signals, each of which represents a pixel map block (420) with the coefficients in a hybrid polynomial. When the pixel map signal is decompressed, the pixel values in the overlap component for each pixel map block (420) are averaged with the pixel values in the overlap component for the adjacent block and replaced by the averaged pixel values in the corresponding pixel map block (420) and the adjacent pixel map block (420).

Abstract: Polynomial processors learn expert system rules, for either business or real-time applications, to improve the robustness and speed of execution of the expert system. One or more polynomial processors are constructed which incorporate the production rules of one or more expert systems. Each polynomial processor is constructed of computing elements or neuron circuits each having only one significant processing element in the form of a multiplier. Each polynomial processor utilizes a training algorithm which does not require repetitive training and which yields a global minimum to each given set of input vectors.

Abstract: A method and system for an FIR filter are provided. A sequence of input signal is converted to a corresponding sequence of log signals. FIR filtering coefficients are then added to each log signal to generate a plurality of term signals. The term signals are then converted to inverse-log signals, and the inverse-log signals are summed to produce an output signal. Log/inverse-log conversions of signals are based on estimating a log/inverse-log function using a second-order polynomial.

Abstract: An enhanced-video circuit for performing non-uniform interpolation of video scan lines is presented. The circuit includes a plurality of interpolation circuits, a memory for storing coefficients, and a control unit. The control unit is programmable to vary the scan line spacing of the output video signal.

Abstract: An anti-lock braking system for a vehicle having a plurality of wheels, and a braking system that includes a brake for braking at least one of the plurality of wheels and a brake valve for controlling a braking pressure in the brake in response to a brake valve signal, includes a plurality of wheel speed sensors for generating a plurality of input signals. A polynomial processor, in communication with the plurality of wheel speed sensors, generates a control signal based on a nonlinear polynomial function of the input signal. A post-processor generates the Brake valve signal based on the control signal so as to provide cyclic control of the braking pressure in the brake.

Abstract: In an auto-tuning controller the initial values of control coefficients are found by fitting a control polynomial to control transfer characteristic data. The values are then tuned using a descent-based optimization method.

Abstract: An accumulator is provided which includes a plurality of summing circuits, a plurality of switches, and a control unit for controlling the transmission of data generated by the summing circuits. Each summing circuit generates intermediate sums and includes a port for transmitting the intermediate sums. The switches are connected between the ports of the summing circuits. The control unit is programmable to operate the switches and enable the ports at various times, thus allowing the accumulator to be configured to perform any of a variety of summing operations.

Abstract: In a speech-recognition system having a plurality of classifiers, a voting window includes a sequence of outputs from each of the classifiers. For each classifier, a voting sum is generated corresponding to the voting window. A spoken sound is identified by determining which classifier corresponds to the greatest voting sum.

Abstract: An auto-scaling controller and a method for use therefor is provided. The control inputs and the control coefficients are multiplied by scaling values. The scaling values are then tuned using a descent-based optimization method in order to optimize system performance.

Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).

Abstract: A method of analyzing data, particularly a speech signal, first pre-processes the signal by performing analog-to-digital conversion and cepstral analysis, producing a sequence of data frames. Then the sequence of data frames is partitioned into a plurality of data blocks. The data blocks may be subjected to further analysis, for example, by introducing them to a plurality of neural networks. The system may be implemented using either hardware or software or a combination thereof.

Abstract: A video signal is converted into compressed frame signals, each comprising a coefficient signal of block coefficient signals for each frame in a video image. Each of the block coefficient signals represents the pixels in a pixel map block (420) with the coefficients in a hybrid polynomial. The hybrid polynomial contains discrete cosine terms, a constant term separated from the discrete cosine terms, and polynomial terms extracted from the discrete cosine terms. Each block coefficient signal contains a background component representing a coefficient of the constant term, a linear component representing the coefficients of the polynomial terms, and a nonlinear component representing the coefficients of the discrete cosine terms.

Abstract: In a speech-recognition system having a plurality of classifiers, a voting window includes a sequence of outputs from each of the classifiers. At each interval in the voting window, the outputs are compared to determine a winning output. A spoken sound is identified by determining which classifier generates the greatest number of winning outputs in the voting window.

Abstract: Boundaries of spoken sounds in continuous speech are identified by classifying delimitative sounds to provide improved performance in a speech-recognition system. Delimitative sounds, those portions of continuous speech that occur between two spoken sounds, are recognized by the same method used to recognize spoken sounds. Recognition of delimitative sounds is accomplished by training a learning machine to act as a classifier which implements a discriminant function based on a polynomial expansion.

Abstract: A computing device, which may be implemented as an integrated circuit, is constructed of a microprocessor and one or more neural network co-processors. The microprocessor normally executes programs which transfer data to the neural network co-processors, which are used to compute complicated mathematical functions. Direct Memory Access (DMA) is also used to transfer data. Each neural network co-processor interfaces to the microprocessor in a manner substantially similar to that of a conventional memory device. The co-processor does not require any instructions and is configured to execute mathematical operations simply by being pre-loaded with gating functions and weight values. In addition, the co-processor executes a plurality of arithmetic operations in parallel, and the results of such operations are simply read from the co-processor.

Abstract: An artificial neuron, which may be implemented on an integrated circuit, has only one significant processing element in the form of an adder. Inputs are first fed through gating functions to produce gated inputs. These gated inputs are then added together to produce a sum which is added to a weight to produce the neuron output.