Patents by Inventor Shaz Qadeer
Shaz Qadeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220269672Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable storage media for implementing a scalable, secure, efficient, and adaptable distributed digital ledger transaction network. Indeed, the disclosed systems can reduce storage and processing requirements, improve security of implementing computing devices and underlying digital assets, accommodate a wide variety of different digital programs (or “smart contracts”), and scale to accommodate billions of users and associated digital transactions. For example, the disclosed systems can utilize a host of features that improve storage, account/address management, digital transaction execution, consensus, and synchronization processes. The disclosed systems can also utilize a new programming language that improves efficiency and security of the distributed digital ledger transaction network.Type: ApplicationFiled: February 28, 2022Publication date: August 25, 2022Inventors: Samuel Howard Blackshear, Shaz Qadeer, Todd Michael Nowacki, Dario Russi, Runtian Zhou
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Patent number: 10380008Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.Type: GrantFiled: May 16, 2016Date of Patent: August 13, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Rui Wang, Yuchen Zhou, Shuo Chen, Shaz Qadeer, Yuri Gurevich
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Patent number: 10255153Abstract: In various embodiments, methods and systems for testing failover and recovery are provided. Systematic testing of a distributed system is performed, where the systematic testing probabilistically determines a processing order of events to effectuate system states for the plurality of state machines. An iteration of the systematic testing tests one the system states and includes sending a termination message to a state machine; receiving a termination acknowledgment message, the termination message causing the state machine to halt at the state and event of the state machine for the system state; and instantiating a recovery state machine. The recovery state machine is instantiated with a same state and same role as the halted state machine. Results of the systematic testing are verified against an expected outcome, the results being generated by running the distributed system with the instantiated recovery state machine for each iteration of the systematic testing.Type: GrantFiled: October 21, 2016Date of Patent: April 9, 2019Inventors: Narayanan Ganapathy, Shaz Qadeer, Akash Lal
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Publication number: 20180113775Abstract: In various embodiments, methods and systems for testing failover and recovery are provided. Systematic testing of a distributed system is performed, where the systematic testing probabilistically determines a processing order of events to effectuate system states for the plurality of state machines. An iteration of the systematic testing tests one the system states and includes sending a termination message to a state machine; receiving a termination acknowledgment message, the termination message causing the state machine to halt at the state and event of the state machine for the system state; and instantiating a recovery state machine. The recovery state machine is instantiated with a same state and same role as the halted state machine. Results of the systematic testing are verified against an expected outcome, the results being generated by running the distributed system with the instantiated recovery state machine for each iteration of the systematic testing.Type: ApplicationFiled: October 21, 2016Publication date: April 26, 2018Inventors: NARAYANAN GANAPATHY, SHAZ QADEER, AKASH LAL
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Publication number: 20160259718Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Rui WANG, Yuchen ZHOU, Shuo CHEN, Shaz QADEER, Yuri GUREVICH
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Patent number: 9372785Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.Type: GrantFiled: March 7, 2013Date of Patent: June 21, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Rui Wang, Yuchen Zhou, Shuo Chen, Shaz Qadeer, Yuri Gurevich
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Patent number: 9329877Abstract: A symbolic encoding of predicated execution for static verification, based on a plurality of data parallel program instructions, is obtained. A result of static verification of one or more attributes associated with the plurality of data parallel program instructions is obtained, based on the symbolic encoding.Type: GrantFiled: March 18, 2012Date of Patent: May 3, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Alastair Francis Donaldson, Shaz Qadeer
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Patent number: 9063778Abstract: Techniques for providing a fair stateless model checker are disclosed. In some aspects, a schedule is generated to allocate resources for threads of a multi-thread program in lieu of having an operating system allocate resources for the threads. The generated schedule is both fair and exhaustive. In an embodiment, a priority graph may be implemented to reschedule a thread when a different thread is determined not to be making progress. A model checker may then implement one of the generated schedules in the program in order to determine if a bug or a livelock occurs during the particular execution of the program. An output by the model checker may facilitate identifying bugs and/or livelocks, or authenticate a program as operating correctly.Type: GrantFiled: January 9, 2008Date of Patent: June 23, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Madanlal Musuvathi, Shaz Qadeer
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Patent number: 9053227Abstract: A concurrency assertions system disclosed herein provides for atomic evaluation of an assertion expression by locking an assertion lock upon initiating an assertion and thereby protecting the assertion evaluation from concurrent modifications to the variables in the assertion expressions. When a violation of an assertion is detected, the concurrency assertions system ensures that the exception statistics at the time of the assertion violation represents a program state where the assertion is violated, thus improving analysis of assertion violations. Furthermore, the concurrency assertions system continuously evaluates an expression for an assertion for a time period while other threads in the program are being executed.Type: GrantFiled: March 9, 2012Date of Patent: June 9, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Jacob Samuels Burnim, Madanlal Musuvathi, Shaz Qadeer
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Patent number: 9015674Abstract: Various technologies pertaining to answering reachability queries are described herein. A reachability query includes a user-specified destination line of code in source code that is desirably analyzed. A theorem prover is employed to identify an execution path through the source code that reaches the destination line of code. Graphical data is presented to the user that illustrates to the user the execution path through the source code that reaches the destination line of code.Type: GrantFiled: September 28, 2012Date of Patent: April 21, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Robert DeLine, Mike Barnett, Akash Lal, Shaz Qadeer
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Publication number: 20140258986Abstract: A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: MICROSOFT CORPORATIONInventors: Rui Wang, Yuchen Zhou, Shuo Chen, Shaz Qadeer, Yuri Gurevich
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Patent number: 8813043Abstract: This document describes a unified type checker and property checker for a low level program's heap and its types. The type checker can use the full power of the property checker to express and verify subtle, program specific type and memory safety invariants well beyond what the native low level program system can check. Meanwhile, the property checker can rely on the type checker to provide structure and disambiguation for the program's heap, enabling more concise and more powerful type-based specifications. This approach makes use of a fully automated Satisfiability Modulo Theories (SMT) solver and a decision procedure for checking type safety, which means that the programmer's only duty is to provide high-level type and property annotations as part of the original program's source.Type: GrantFiled: December 31, 2008Date of Patent: August 19, 2014Assignee: Microsoft CorporationInventors: Jeremy P. Condit, Shaz Qadeer, Shuvendu K. Lahiri
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Publication number: 20140096112Abstract: Various technologies pertaining to answering reachability queries are described herein. A reachability query includes a user-specified destination line of code in source code that is desirably analyzed. A theorem prover is employed to identify an execution path through the source code that reaches the destination line of code. Graphical data is presented to the user that illustrates to the user the execution path through the source code that reaches the destination line of code.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: Microsoft CorporationInventors: Robert DeLine, Mike Barnett, Akash Lal, Shaz Qadeer
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Publication number: 20130241941Abstract: A symbolic encoding of predicated execution for static verification, based on a plurality of data parallel program instructions, is obtained. A result of static verification of one or more attributes associated with the plurality of data parallel program instructions is obtained, based on the symbolic encoding.Type: ApplicationFiled: March 18, 2012Publication date: September 19, 2013Applicant: MICROSOFT CORPORATIONInventors: Alastair Francis Donaldson, Shaz Qadeer
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Publication number: 20130239120Abstract: A concurrency assertions system disclosed herein provides for atomic evaluation of an assertion expression by locking an assertion lock upon initiating an assertion and thereby protecting the assertion evaluation from concurrent modifications to the variables in the assertion expressions. When a violation of an assertion is detected, the concurrency assertions system ensures that the exception statistics at the time of the assertion violation represents a program state where the assertion is violated, thus improving analysis of assertion violations. Furthermore, the concurrency assertions system continuously evaluates an expression for an assertion for a time period while other threads in the program are being executed.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: Microsoft CorporationInventors: Jacob Samuels Burnim, Madanlal Musuvathi, Shaz Qadeer
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Patent number: 7926035Abstract: Testing multithreaded application programs for errors can be carried out in an efficient and productive manner at least in part by prioritizing thread schedules based on numbers of context switches between threads therein. In particular, each thread schedule in a multithreaded application program can be prioritized based on whether a given thread schedule has the same as or less than some maximum value. A model checker module can then iteratively execute thread schedules that fit within a given context switch maximum value, or a progressively higher value up to some limit. In one implementation, for example, the model checker module executes all thread schedules that have zero preempting context switches, then all thread schedules that have only one preempting context switch, etc. Most errors in an application program can be identified by executing only those thread schedule with relatively few preempting context switches.Type: GrantFiled: April 24, 2007Date of Patent: April 12, 2011Assignee: Microsoft CorporationInventors: Madanlal S. Musuvathi, Shaz Qadeer
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Patent number: 7779382Abstract: Validity of one or more assertions for any concurrent execution of a plurality of software instructions with at most k?1 context switches can be determined. Validity checking can account for execution of the software instructions in an unbounded stack depth scenario. A finite data domain representation can be used. The software instructions can be represented by a pushdown system. Validity checking can account for thread creation during execution of the plurality of software instructions.Type: GrantFiled: December 10, 2004Date of Patent: August 17, 2010Assignee: Microsoft CorporationInventors: Niels Jakob Rehof, Shaz Qadeer
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Patent number: 7752605Abstract: A data race detection system is described which precisely identifies data races in concurrent programs. The system and techniques described utilize locksets to maintain information while searching through executions of a concurrent program. The locksets are updated according to program statements in the concurrent program. The dynamic updating of the locksets, combined with a less conservative approach then used in existing lockset data race detection techniques, allows the technique to be precise; that is, the technique does not report false positives when searching a program.Type: GrantFiled: April 12, 2006Date of Patent: July 6, 2010Assignee: Microsoft CorporationInventors: Shaz Qadeer, Tayfun Elmas
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Publication number: 20100169868Abstract: This document describes a unified type checker and property checker for a low level program's heap and its types. The type checker can use the full power of the property checker to express and verify subtle, program specific type and memory safety invariants well beyond what the native low level program system can check. Meanwhile, the property checker can rely on the type checker to provide structure and disambiguation for the program's heap, enabling more concise and more powerful type-based specifications. This approach makes use of a fully automated Satisfiability Modulo Theories (SMT) solver and a decision procedure for checking type safety, which means that the programmer's only duty is to provide high-level type and property annotations as part of the original program's source.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: Microsoft CorporationInventors: Jeremy P. Condit, Shaz Qadeer, Shuvendu K. Lahiri
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Patent number: 7650595Abstract: Described techniques and tools help model checking scale to large programs while reducing missed errors. In particular, described techniques and tools help reduce the state space of concurrent programs without depending on cycle detection and without scheduling execution of postponed threads at all cycles. For example, described techniques and tools use a type of partial-order reduction called transaction-based reduction to reduce program state space. Analysis is performed at commit points to determine whether to schedule delayed threads.Type: GrantFiled: April 29, 2005Date of Patent: January 19, 2010Assignee: Microsoft CorporationInventors: Shaz Qadeer, Sriram K. Rajamani, Vladimir A. Levin, Robert Palmer