Abstract: A bus pipeline structure comprises: an n-channel multiplexer at a transmitting end works in an n times of clock domain of a transmitting chiplet; the n-channel multiplexer sends a data flow from the transmitting chiplet to an n-channel de-multiplexer at a receiving end, the n-channel de-multiplexer inputs the received data flow into a first register in an idle state among at least two registers at the receiving end, the first register outputs the received data flow to a receiving chiplet; after a receiving state machine at the receiving end determines that the n-channel de-multiplexer sends the received data flow to the first register, the receiving state machine at the receiving end sends a bus release flag to a transmitting state machine at the transmitting end, and the transmitting state machine receiving the bus release flag controls an n-channel multiplexer to transmit the data flow in a next clock cycle.

Abstract: A hybrid system fabric is disclosed for use within a chiplet SOC. The hybrid system fabric facilitates fast communication between a real-time system, a host system, chiplets, memory systems, and other shared resources within the chiplet SOC. The hybrid system fabric supports both concurrent high throughput data processing and high computing power.

Abstract: A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.

Abstract: A serial bus is disclosed. In one embodiment, data is transmitted over the serial bus using quadrature amplitude modulation. Other information, including synchronization information, is sent concurrently with the data using a different modulation technique, such as baseband or DC amplitude modulation.

Abstract: A high performance, low power, and cost effective multiple channel cache-system memory system is disclosed.

Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range communication (less than a few inches) from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. Differential current mode modulation in the transmitter, and demodulation in the receiver, are utilized which reduce latency and power-consumption while increasing manufacturing yields and resilience to process variations.

Abstract: A serial bus is disclosed. In one embodiment, data is transmitted over the serial bus using quadrature amplitude modulation. Other information, including synchronization information, is sent concurrently with the data using a different modulation technique, such as baseband or DC amplitude modulation.

Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.

Abstract: A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

Abstract: A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency quadrature amplitude modulation (QAM) mechanism for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. The serializer has multiple digital-to-analog converters (DACs) whose outputs are directed to QAM mixer inputs, within QAMs at multiple frequencies, whose outputs are summed into a single analog signal for communication over an I/O connection. The de-serializer amplifies the analog signal which is received by QAM mixers at different frequencies, whose outputs are low pass filtered and converted back to parallel digital data bits.

Abstract: A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range is selected much broader than the application warrants so that sufficient range is still provided despite VCO process variations. The inventive VCO is able to substantially eliminate the effects of process variation by utilizing a calibration circuit and process, so that variation in VCO device operation is minimized despite substantial process variation. Accordingly, the inventive VCO device is subject to reduced levels of jitter as its range need not be utilized for overcoming process variation arising during device fabrication.

Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range wired RF communication from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. During a phase calibration cycle, a phase adjustment controller in the transmitter interoperates with a phase adjustment controller in the receiver, to adjust a phase locked-loop (PLL) circuit to correct for the phase delay arising in response to signal propagation between transmitter and receiver.

Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range communication (less than a few inches) from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. Differential current mode modulation in the transmitter, and demodulation in the receiver, are utilized which reduce latency and power-consumption while increasing manufacturing yields and resilience to process variations.

Abstract: A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range is selected much broader than the application warrants so that sufficient range is still provided despite VCO process variations. The inventive VCO is able to substantially eliminate the effects of process variation by utilizing a calibration circuit and process, so that variation in VCO device operation is minimized despite substantial process variation. Accordingly, the inventive VCO device is subject to reduced levels of jitter as its range need not be utilized for overcoming process variation arising during device fabrication.

Abstract: A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

Abstract: A serializer and de-serializer circuit which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency quadrature amplitude modulation (QAM) mechanism for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. The serializer has multiple digital-to-analog converters (DACs) whose outputs are directed to QAM mixer inputs, within QAMs at multiple frequencies, whose outputs are summed into a single analog signal for communication over an I/O connection. The de-serializer amplifies the analog signal which is received by QAM mixers at different frequencies, whose outputs are low pass filtered and converted back to parallel digital data bits.

Abstract: The MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing the digital XOR function. The MOS analog comparator provided comprises N number of MOS analog XOR means for performing the digital XOR function and a MOS analog NOR means for performing the digital NOR function.

Abstract: The MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing the digital XOR function. The MOS analog comparator provided comprises N number of MOS analog XOR means for performing the digital XOR function and a MOS analog NOR means for performing the digital NOR function.

Abstract: This invention relates to the MOS analog multi-bit comparator amplifier for performing the high speed digital multi-bit comparator function which is required, for example, in Cache Tag Random Access Memory of a computer system, and to the MOS analog XOR amplifier for performing the digital XOR function. The MOS analog comparator provided comprises N number of MOS analog XOR means for performing the digital XOR function and a MOS analog NOR means for performing the digital NOR function.

Abstract: A ground bouncing reducing circuit comprises a first control means, a second control means and an output means for generating an output signal at a fourth output terminal. The first control means generates a first control signal at a first output terminal and a second control signal at a second output terminal in response to an input signal. The first control signal and the second control signal are not asserted at the same time. The second control means generates a third control signal at a third output terminal in response to the first control signal and the second control signal. The ground bouncing phenomenon is reduced when the output signal changes state.