Patents by Inventor Sheau-Jiung Lee

Sheau-Jiung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5218246
    Abstract: This invention relates to the MOS analog XOR amplifier for performing the digital XOR function.
    Type: Grant
    Filed: September 14, 1990
    Date of Patent: June 8, 1993
    Assignee: Acer, Incorporated
    Inventors: Sheau-Jiung Lee, Gene Yang
  • Patent number: 5206833
    Abstract: A pipelined random access memory for use in color display system. A multiplexer, including a video port and a microprocessor port, provides the RAM input. A memory array, a sensing latch and an I/O latch, in addition to the multiplexer, provide the pipeline architecture, enabling the random memory to be accessed at three different locations simultaneously. Thus, with the same memory speed, the data throughput of this RAM is triple that in the known art. A clock circuit is constructed to generate extremely stable internal clock pulses so that the interval of each clock pulse varies automatically according to the IC manufacturing process and the ambient temperature in use, thereby adapting to the appropriate precharging interval related to the memory array, multiplexer, and sensing latch.
    Type: Grant
    Filed: March 13, 1991
    Date of Patent: April 27, 1993
    Assignee: Acer Incorporated
    Inventor: Sheau-Jiung Lee
  • Patent number: 5004938
    Abstract: A MOS (preferably CMOS type) analog NOR amplifier suitable for use in building a programmable array logic (PAL) or the like, or for other usages. The analog NOR amplifier consists of a reference MOS transistor and first pull-up means at one branch and a plurality of input MOS transistors and second pull-up means at another branch with a constant current source connected to the source terminals of these MOS transistors, which forms a configuration similar to a differential amplifier. With the gate terminals of the plurality of input MOS transistors as logic input ends, the drain terminals of the same will act as the output end of a standard NOR gate and the drain terminal of the reference MOS transistor will behave as the output end of a standard OR gate.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: April 2, 1991
    Assignee: Acer Incorporated
    Inventor: Sheau-Jiung Lee