Patents by Inventor Sheila Marie L. Alvarez

Sheila Marie L. Alvarez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090273062
    Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.
    Type: Application
    Filed: July 6, 2009
    Publication date: November 5, 2009
    Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow, Sheila Marie L. Alvarez
  • Patent number: 7575956
    Abstract: A method for fabricating a semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: August 18, 2009
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Virgil Cotoco Ararao, Il Kwon Shim, Seng Guan Chow, Sheila Marie L. Alvarez
  • Patent number: 7482683
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 27, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Erick Dahilig, Sheila Marie L. Alvarez, Robinson Quiazon, Jose Alvin Caparas
  • Publication number: 20080315411
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Publication number: 20080284038
    Abstract: An integrated circuit package system is provided including forming a perimeter paddle having a first external interconnect extending therefrom, mounting an integrated circuit die over the perimeter paddle, connecting a second external interconnect and the integrated circuit die, and encapsulating the integrated circuit die and the perimeter paddle with the first external interconnect exposed.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 20, 2008
    Inventors: Antonio B. Dimaano, JR., Sheila Marie L. Alvarez
  • Publication number: 20080272487
    Abstract: A wire bond system including providing an integrated circuit die with a bond pad thereon, forming a soft bump on the bond pad, and wire bonding a hard-metal wire on the soft bump.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 6, 2008
    Inventors: Il Kwon Shim, Hun Teak Lee, Sheila Marie L. Alvarez, Gyung Sik Yun, Heap Hoe Kuan
  • Patent number: 7443015
    Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: October 28, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Sheila Marie L. Alvarez, Jose Alvin Caparas, Robinson Quiazon
  • Patent number: 7414318
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: August 19, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Hin Hwa Goh, Robinson Quiazon
  • Patent number: 7352055
    Abstract: A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: April 1, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Sheila Rima C. Magno
  • Patent number: 7327025
    Abstract: An electronic device having a substrate carrier is provided. A semiconductor connected to the substrate carrier. A heat spreader having upper and lower surfaces and legs recessed below the lower surface is connected to the substrate carrier. The Z-dimension between the heat spreader and the substrate carrier is maintained over substantially the entire area of the substrate carrier.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 5, 2008
    Assignee: St Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Virgil Cotoco Ararao
  • Patent number: 7250685
    Abstract: The present invention provides an etched leadframe flipchip package system comprising forming a leadframe comprises forming contact leads and etching a plurality of multiple dotted grooves on the contact leads, and attaching a flipchip integrated circuit having solder interconnects on the contact leads between each of the plurality of the multiple dotted grooves.
    Type: Grant
    Filed: February 4, 2006
    Date of Patent: July 31, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Hin Hwa Goh, Robinson Quiazon
  • Patent number: 7169641
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate having a plurality of contacts with solder bump contact areas that are unmasked. A plurality of underfill bumps is formed on the plurality of contacts selectively in the solder bump contact areas. A die having a plurality of solder bumps is positioned on the substrate so the plurality of solder bumps is substantially vertically aligned with the plurality of underfill bumps. The plurality of solder bumps is pressed into the plurality of underfill bumps until the plurality of solder bumps contacts the plurality of contacts. The plurality of solder bumps is reflowed. The die, the plurality of solder bumps, and the plurality of contacts are encapsulated to expose a lower surface of the plurality of contacts.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: January 30, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Romeo Emmanuel P. Alvarez
  • Patent number: 7153725
    Abstract: A method for fabricating a semiconductor package with a substrate in a strip format is provided. Semiconductor devices are attached in a strip format to the substrate, and a thermal interface material is applied to the semiconductor devices. A flat panel heat spreader is attached to each semiconductor device. The semiconductor devices are encapsulated with open encapsulation, leaving the surface of the flat panel heat spreader opposite the substrate externally exposed. Individual semiconductor packages are then singulated from the strip format.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 26, 2006
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Tie Wang, Virgil Cotoco Ararao, Il Kwon Shim, Sheila Marie L. Alvarez
  • Patent number: 7148086
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package include a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: December 12, 2006
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Sheila Marie L. Alvarez, Sheila Rima C. Magno
  • Patent number: 6775140
    Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: August 10, 2004
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh
  • Publication number: 20040075987
    Abstract: A method for fabricating a semiconductor device heat spreader from a unitary piece of metallic material. The metallic material is stamped to form a unitary heat spreader having an upper heat dissipation region, a lower substrate contact region, and supports connecting the upper heat dissipation region and the lower substrate contact region. A recess is formed within the supports and the upper and lower regions for receiving a semiconductor device.
    Type: Application
    Filed: May 7, 2003
    Publication date: April 22, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Seng Guan Chow, Virgil Cotoco Ararao, Sheila Marie L. Alvarez, Roger Emigh