Abstract: A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness.

Abstract: An enhancement-mode inverter includes a load transistor and a drive transistor. The load transistor has a bottom gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness less than the load dielectric thickness. The first source is electrically connected to the second drain and the first gate is electrically connected to the first drain. The load gate dielectric and the drive gate dielectric are part of a common shared dielectric stack.

Abstract: An enhancement-depletion-mode inverter includes a load transistor and a drive transistor. The load transistor has a top gate architecture with a first source, a first drain, a load channel region, a first semiconductor layer, and a first gate electrode. A load gate dielectric is in the load channel region, and has a load dielectric thickness. The load transistor is configured to operate in a depletion mode. The drive transistor has a bottom gate architecture with a second source, a second drain, a drive channel region, a second semiconductor layer, and a second gate electrode. A drive gate dielectric is in the drive channel region, and has a drive dielectric thickness that is different from the load dielectric thickness. The drive transistor is configured to operate in a normal mode or an enhancement mode. The first source is electrically connected to the second drain and the first gate.

Abstract: A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor.

Abstract: A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top, and an edge along the height dimension. A cap covers the top of the post and extends to a distance beyond the edge of the post to define a reentrant profile. A conformal conductive gate layer is located on the edge of the post in the reentrant profile and not over the cap, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with a first portion of the semiconductor layer over the cap and a second portion of the semiconductor layer not over the post, respectively.

Abstract: A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.

Abstract: A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap.

Abstract: A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.

Abstract: A vertical transistor includes an electrically conductive gate structure having a reentrant profile in contact with a substrate. A conformal gate insulating layer is in contact with the gate structure in the reentrant profile. A conformal semiconductor layer is in contact with the conformal gate insulating layer. A first electrode is in contact with a first portion of the conformal semiconductor layer over the electrically conductive gate structure. A second electrode is in contact with a second portion of the conformal semiconductor layer and separated vertically from the first electrode. The vertical TFT has a multilayer insulating structure that is in contact with at least the conformal semiconductor layer in the reentrant profile. The multilayer insulating structure includes an inorganic dielectric layer and a polymer structure in contact with the conformal semiconductor layer in the reentrant profile.

Abstract: A method of producing a patterned polymeric insulator includes providing a substrate. A patterned polymeric inhibitor is provided on the substrate. An inorganic thin film is deposited using an atomic layer deposition process on the substrate in an area where the patterned polymeric inhibitor is absent. A material layer is deposited over the inorganic thin film and the patterned polymeric inhibitor.

Abstract: A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate.

Abstract: A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile.

Abstract: Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. Exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post defining a reentrant profile. A conformal conductive gate layer and a conformal dielectric layer on the gate layer are formed in the reentrant profile. A conformal semiconductor layer is formed on the dielectric layer. First and second electrodes are formed in contact with a first portion (over the cap) and a second portion (not over the post) of the semiconductor layer.

Abstract: A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure. A polymeric resist is printed that wicks along the reentrant profile of the gate structure. The conformal conductive inorganic thin film is etched in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.

Abstract: A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure and in the reentrant profile. A photoresist is deposited on the conformal conductive inorganic thin film over the gate structure and filling the reentrant profile. The photoresist is exposed from a side of the photoresist opposite the substrate allowing the photoresist in the reentrant profile to remain unexposed. The conformal conductive inorganic thin film is etched in areas not protected by the photoresist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.

Abstract: A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively.

Abstract: A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.

Abstract: A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top portion of the post which extends a distance beyond a bottom portion of the post in a direction parallel to the substrate to define a reentrant profile. A conformal conductive gate layer is located on an edge of the post in the reentrant profile and not over the top portion of the post, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with first and second portions of the semiconductor layer over the top portion of the post and not over the top portion of the post, respectively.

Abstract: A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure and in the reentrant profile. A photoresist is deposited on the conformal conductive inorganic thin film over the gate structure and filling the reentrant profile. The photoresist is exposed from a side of the photoresist opposite the substrate allowing the photoresist in the reentrant profile to remain unexposed. The conformal conductive inorganic thin film is etched in areas not protected by the photoresist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.

Abstract: Producing vertically separated electrodes includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. The exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post to define a reentrant profile. A polymeric inhibitor is provided in the reentrant profile. A conductive inorganic thin film is deposited where the polymeric inhibitor is absent using an atomic layer deposition process to form a first electrode located over the cap and a second electrode over the substrate and not over the post.