Abstract: A vertical transistor includes a substrate and an electrically conductive gate structure having a top surface and including a reentrant profile. A conformal electrically insulating layer that maintains the reentrant profile is in contact with the electrically conductive gate structure and at least a portion of the substrate. A conformal semiconductor layer that maintains the reentrant profile is in contact with the conformal electrically insulating layer. An electrode that extends into the reentrant profile is in contact with a first portion of the semiconductor layer. Another electrode is vertically spaced apart from the electrode, overlaps a portion of the electrode that extends into the reentrant profile, is in contact with a second portion of the semiconductor material layer over the top surface of the electrically conductive gate structure, and is within the reentrant profile.

Abstract: A method of forming a gate layer of a thin film transistor includes providing a substrate including a gate structure having a reentrant profile. A conformal conductive inorganic thin film is deposited over the gate structure. A polymeric resist is printed that wicks along the reentrant profile of the gate structure. The conformal conductive inorganic thin film is etched in areas not protected by the polymeric resist to form a patterned conductive gate layer located in the reentrant profile of the gate structure.

Abstract: Fabricating a vertical transistor includes providing a structural polymer layer on a substrate. A patterned inorganic thin film is formed on the structural polymer layer, leaving exposed portions of the structural polymer layer not under the inorganic thin film. Exposed portions of the structural polymer layer and portions of the structural polymer layer between the patterned inorganic thin film and the substrate are removed to form a structural polymer post having an inorganic cap that extends beyond an edge of the structural polymer post defining a reentrant profile. A conformal conductive gate layer and a conformal dielectric layer on the gate layer are formed in the reentrant profile. A conformal semiconductor layer is formed on the dielectric layer. First and second electrodes are formed in contact with a first portion (over the cap) and a second portion (not over the post) of the semiconductor layer.

Abstract: A multiple vertical transistor device includes a polymeric material post on a substrate. An inorganic material cap extends beyond first and second edge of the post to define first and second reentrant profiles. First and second portions of a conformal conductive gate layer define first and second gates in the first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the first and second reentrant profiles and is in contact with the first and second gates. First and second portions of a semiconductor layer, maintaining the first and second reentrant profiles, are in contact with the conformal electrically insulating layer that is in contact with the first and second gates, respectively. The first and second portions of the semiconductor layer are electrically independent from each other. First and second electrodes are associated with the first gate. Third and fourth electrodes are associated with the second gate.

Abstract: A method of producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal insulating material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the insulating material layer. A deposition inhibiting material is deposited over a portion of the substrate and the conductive gate structure including filling the reentrant profile. A portion of the deposition inhibiting material is removed without removing all of the deposition inhibiting material from the reentrant profile. A plurality of electrodes is formed by depositing an electrically conductive material layer on portions of the semiconductor material layer using a selective area deposition process in which the electrically conductive material layer is not deposited on the deposition inhibiting material remaining in the reentrant profile.

Abstract: A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface.

Abstract: A thin film transistor includes a post on a substrate. The post has a height dimension extending away from the substrate to a top, and an edge along the height dimension. A cap covers the top of the post and extends to a distance beyond the edge of the post to define a reentrant profile. A conformal conductive gate layer is located on the edge of the post in the reentrant profile and not over the cap, and includes a portion that extends along the substrate. A conformal insulating layer is on the gate layer in the reentrant profile. A conformal semiconductor layer is on the insulating layer in the reentrant profile. First and second electrodes are located in contact with a first portion of the semiconductor layer over the cap and a second portion of the semiconductor layer not over the post, respectively.

Abstract: Fabricating a vertical thin film transistor includes printing a polymeric inhibitor in a cap pattern on a structural polymer layer on a substrate. A polymeric inhibitor is printed in a gate pattern on the substrate, in a dielectric pattern on the substrate, in a semiconductor pattern on a patterned conformal dielectric layer, and in an electrode pattern. The electrode pattern includes an open area over a portion of a reentrant profile that allows the polymeric inhibitor to wick along the reentrant profile in the open area. Fabrication of the vertical transistor also includes depositing an inorganic thin film, a first conductive thin film, a dielectric thin film, a semiconductor thin film, and a second conductive thin film using an atomic layer deposition (ALD) process.

Abstract: A device with multiple vertical transistors includes a substrate and an electrically conductive gate structure including first and second edges opposite each other and including first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the reentrant profiles and is in contact with the gate. A conformal semiconductor layer maintains the reentrant profiles and is in contact with the insulating layer. First and second electrodes are in contact with first and second portions of the semiconductor and adjacent to the first and second reentrant profiles, respectively. A third electrode is in contact with a third portion of the semiconductor on a top of the gate structure. The first and third electrodes and the second and third electrodes define ends of first and second channels of first and second transistors, respectively. First and second lines, extending between the ends of the first and second channels, are not parallel.

Abstract: Fabricating a vertical thin film transistor includes printing a polymeric inhibitor in a cap pattern on a structural polymer layer on a substrate. A polymeric inhibitor is printed in a gate pattern on the substrate, in a dielectric pattern on the substrate, in a semiconductor pattern on a patterned conformal dielectric layer, and in an electrode pattern. The electrode pattern includes an open area over a portion of a reentrant profile that allows the polymeric inhibitor to wick along the reentrant profile in the open area. Fabrication of the vertical transistor also includes depositing an inorganic thin film, a first conductive thin film, a dielectric thin film, a semiconductor thin film, and a second conductive thin film using an atomic layer deposition (ALD) process.

Abstract: A device with multiple vertical transistors includes a substrate and an electrically conductive gate structure including first and second edges opposite each other and including first and second reentrant profiles, respectively. A conformal electrically insulating layer maintains the reentrant profiles and is in contact with the gate. A conformal semiconductor layer maintains the reentrant profiles and is in contact with the insulating layer. First and second electrodes are in contact with first and second portions of the semiconductor and adjacent to the first and second reentrant profiles, respectively. A third electrode is in contact with a third portion of the semiconductor on a top of the gate structure. The first and third electrodes and the second and third electrodes define ends of first and second channels of first and second transistors, respectively. First and second lines, extending between the ends of the first and second channels, are not parallel.

Abstract: A transistor includes a polymeric material post on a substrate. An inorganic material cap, covering the post, extends beyond an edge of the post to define a reentrant profile. A conformal conductive material gate layer is over the edge of the post in the reentrant profile. A conformal insulating material layer is on the gate layer in the reentrant profile. A conformal semiconductor material layer is on the insulating material layer in the reentrant profile. A first electrode is in contact with a first portion of the semiconductor layer over the cap. A second electrode is in contact with a second portion of the semiconductor layer over the substrate and not over the post, and adjacent to the edge of the post in the reentrant profile such that a distance between the first electrode and second electrode is greater than zero when measured orthogonally to the substrate surface.

Abstract: Producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal dielectric material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the dielectric material layer, over the conductive gate structure. An electrode is formed located over the conductive gate structure and in contact with a first portion of the semiconductor layer and another electrode is formed vertically separated from the electrode and located in contact with a second portion of the semiconductor layer by printing an inhibitor that wicks along the reentrant profile of the conductive gate structure and depositing a conductive inorganic thin film using an atomic layer deposition process where the inhibitor is absent to form a channel in the semiconductor layer along the reentrant profile between the electrodes by inhibiting deposition of conductive material between the electrodes with the wicked inhibitor.

Abstract: A method of making an embossed micro-structure includes providing a transfer substrate, an emboss substrate, and an embossing stamp having one or more stamp structures. Transfer material is coated on the transfer substrate. The transfer material on the transfer substrate is contacted with the stamp structures to adhere transfer material to the stamp structures. A curable emboss layer is coated on the emboss substrate. The stamp structures and adhered transfer material are contacted to the curable emboss layer on the emboss substrate to emboss a micro-structure in the curable emboss layer and transfer the transfer material to the embossed micro-structure. The curable emboss layer is cured to form a cured emboss layer having embossed micro-structures corresponding to the stamp structures and having transfer material in the embossed micro-structures. The stamp structures is removed from the cured emboss layer, substantially leaving the transfer material in the micro-structure.

Abstract: An embossed micro-structure includes an emboss substrate having a cured emboss layer formed thereon. The cured emboss layer has a cured-layer surface opposite the substrate and one or more micro-channels embossed in the cured emboss layer extending from the cured-layer surface into the cured emboss layer toward the substrate. A cured transfer material is located on, in, or beneath the micro-channels.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: A method of making an embossed micro-structure includes providing a transfer substrate, an emboss substrate, and an embossing stamp having one or more stamp structures. Transfer material is coated on the transfer substrate. The transfer material on the transfer substrate is contacted with the stamp structures to adhere transfer material to the stamp structures. A curable emboss layer is coated on the emboss substrate. The stamp structures and adhered transfer material are contacted to the curable emboss layer on the emboss substrate to emboss a micro-structure in the curable emboss layer and transfer the transfer material to the embossed micro-structure. The curable emboss layer is cured to form a cured emboss layer having embossed micro-structures corresponding to the stamp structures and having transfer material in the embossed micro-structures. The stamp structures is removed from the cured emboss layer, substantially leaving the transfer material in the micro-structure.