Patents by Inventor Sheldon Douglas
Sheldon Douglas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047387Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.Type: ApplicationFiled: October 20, 2023Publication date: February 8, 2024Inventors: Alexei Sadovnikov, Sheldon Douglas Haynie, Ujwal Radhakrishna
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Publication number: 20230411452Abstract: A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.Type: ApplicationFiled: May 31, 2022Publication date: December 21, 2023Inventors: Sheldon Douglas Haynie, Alexei Sadovnikov, Brian Goodlin
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Publication number: 20230387260Abstract: A method includes forming a gate on a semiconductor layer of a substrate. A hard mask is formed over the gate and the semiconductor layer to expose a portion of the semiconductor layer. The exposed portion of the semiconductor layer is isotropically etched away to form a recess having a depth. A first selective epitaxial growth of a first semiconductor material doped with a first dopant is performed on the semiconductor layer in the recess. A second selective epitaxial growth of a second semiconductor material doped with a second dopant is performed on the first semiconductor material in the recess. The hard mask is then removed.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Inventors: Sheldon Douglas HAYNIE, Alexei SADOVNIKOV
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Patent number: 11830830Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.Type: GrantFiled: May 12, 2021Date of Patent: November 28, 2023Assignee: Texas Instruments IncorporatedInventors: Alexei Sadovnikov, Sheldon Douglas Haynie, Ujwal Radhakrishna
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Publication number: 20230352580Abstract: A semiconductor device includes a semiconductor substrate including a corrugated surface. A body has a first conductivity type and includes a portion extending continuously along the corrugated surface. A gate dielectric layer is on the body and extends continuously along the corrugated surface. A gate is on the gate dielectric layer, the gate extending continuously along the corrugated surface. A corrugated conformal drift region has a second conductivity type opposite from the first conductivity type, and is on and conformal with the corrugated surface of the semiconductor substrate, and extends continuously along the corrugated surface. A source has the second conductivity type and includes a portion extending continuously along the corrugated surface, the source being in contact with the body. A drain contact region electrically coupled to the drift region and having the second conductivity type.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Sheldon Douglas HAYNIE, Scott SUMMERFELT
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Patent number: 11527617Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.Type: GrantFiled: March 15, 2021Date of Patent: December 13, 2022Assignee: Texas Instruments IncorporatedInventors: Sheldon Douglas Haynie, Alexei Sadovnikov
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Publication number: 20220367388Abstract: A microelectronic device includes a doped region of semiconductor material having a first region and an opposite second region. The microelectronic device is configured to provide a first operational potential at the first region and to provide a second operational potential at the second region. The microelectronic device includes field plate segments in trenches extending into the doped region. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuitry is configured to apply bias potentials to the field plate segments. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region.Type: ApplicationFiled: May 12, 2021Publication date: November 17, 2022Inventors: Alexei Sadovnikov, Sheldon Douglas Haynie, Ujwal Radhakrishna
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Publication number: 20220140129Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Inventor: Sheldon Douglas Haynie
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Patent number: 11257948Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.Type: GrantFiled: September 6, 2019Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sheldon Douglas Haynie
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Publication number: 20220037468Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.Type: ApplicationFiled: March 15, 2021Publication date: February 3, 2022Inventors: Sheldon Douglas Haynie, Alexei Sadovnikov
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Patent number: 10978559Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.Type: GrantFiled: August 3, 2020Date of Patent: April 13, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sheldon Douglas Haynie, Alexei Sadovnikov
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Publication number: 20210074839Abstract: Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.Type: ApplicationFiled: September 6, 2019Publication date: March 11, 2021Inventor: Sheldon Douglas Haynie
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Patent number: 10886418Abstract: An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.Type: GrantFiled: February 21, 2019Date of Patent: January 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sheldon Douglas Haynie
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Publication number: 20200274002Abstract: An IC with a split-gate transistor includes a substrate doped the second conductivity type having a semiconductor surface layer doped the first conductivity type. The transistor includes a first doped region formed as an annulus, a second doped region including under the first doped region, and a third doped region under the second doped region, all coupled together and doped the second conductivity type. A fourth doped region doped the first conductivity type is above the third doped region. A fifth doped region doped the first conductivity type is outside the annulus. Sixth doped regions doped the first conductivity type include a first sixth doped region surrounded by the annulus in the semiconductor surface layer and a second sixth doped region in the fifth doped region. Field oxide includes a field oxide portion between the fifth and the first doped region. A field plate is on the field oxide portion.Type: ApplicationFiled: February 21, 2019Publication date: August 27, 2020Applicant: Texas Instruments IncorporatedInventor: Sheldon Douglas Haynie
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Publication number: 20160244346Abstract: A boiler blowdown recycle method and system for increasing recycle and water recovery percentages for steam generation units used in thermal hydrocarbon recovery processes such as SAGD and CSS methods. Blowdown from a steam generating unit is elevated to supercritical temperatures and pressures, and an oxidizing agent added, thereby oxidizing organic and inorganic compounds in the blowdown and simultaneously reducing solubility of inorganics within the blowdown allowing them to precipitate out or be more easily separated therefrom, leaving a purified stream.Type: ApplicationFiled: October 17, 2014Publication date: August 25, 2016Inventors: Rodger Francesco Bernar, Sheldon Douglas
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Patent number: 6890826Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.Type: GrantFiled: August 23, 2002Date of Patent: May 10, 2005Assignee: Texas Instruments IncorporatedInventor: Sheldon Douglas Haynie
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Publication number: 20040036145Abstract: A method of manufacturing a bipolar junction transistor results in an integrated polysilicon base contact and field plate element minimally spaced from a polysilicon emitter contact by using a single mask to define respective openings for these elements. In particular, a dielectric layer is deposited on a semiconductor wafer and has two openings defined by a single masking step, one opening above an emitter region and a second opening above a base-collector junction region. Polysilicon is deposited on the dielectric layer and selectively doped in the areas of the openings. Thus for an NPN transistor for example, the area above the emitter opening is doped N type and the area above the base/field plate opening is doped P type. The doped polysilicon is patterned and etched to leave a polysilicon emitter contact and an integrated polysilicon base contact and field plate within the respective openings.Type: ApplicationFiled: August 23, 2002Publication date: February 26, 2004Applicant: Texas Instruments IncorporatedInventor: Sheldon Douglas Haynie