Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated chip. The method includes forming a bottom electrode structure over one or more interconnect layers disposed within one or more stacked inter-level dielectric (ILD) layers over a substrate. The bottom electrode structure has an upper surface having a noble metal. A diffusion barrier film is formed over the bottom electrode structure. A data storage film is formed onto the diffusion barrier film, and a top electrode structure is over the data storage film. The top electrode structure, the data storage film, the diffusion barrier film, and the bottom electrode structure are patterned to define a memory device.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes forming a bottom electrode over a substrate. A first switching layer is formed on the bottom electrode. The first switching layer comprises a dielectric material doped with a first dopant. A second switching layer is formed over the first switching layer. An atomic percentage of the first dopant in the second switching layer is less than an atomic percentage of the first dopant in the first switching layer. A top electrode is formed over the second switching layer.

Abstract: The present disclosure relates to a LiDAR. An embodiment of the present invention realizes a control function, a processing function, an emitting function, a receiving function, and an interface function of the LiDAR via each independent board to prevent components from causing a heat accumulation effect. In addition, according to the embodiments of the present disclosure, the digital plate for digital signal processing and the analog plate for analog signal processing are separately arranged to reduce electromagnetic interference between analog signals and digital signals, thereby further reducing the internal interference of the LiDAR.

Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode over the bottom electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the top electrode and the switching layer. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

Abstract: A method of depositing a layer on a semiconductor workpiece is disclosed. The method includes placing the semiconductor workpiece on a wafer chuck in a processing chamber, introducing a first precursor into the processing chamber, introducing a second precursor into the processing chamber, and while the second precursor is in the processing chamber, applying radiation to the semiconductor workpiece, whereby a surface of the semiconductor workpiece is heated. The method also includes, while the second precursor is in the processing chamber, applying a voltage bias to the wafer chuck.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.

Abstract: A semiconductor device includes a bottom electrode, a top electrode, a switching layer and a diffusion harrier layer. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The diffusion barrier layer is between the bottom electrode and the switching layer to obstruct diffusion of ions between the switching layer and the bottom electrode.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure disposed between a top electrode and a bottom electrode. The data storage structure includes a lower switching layer overlying the bottom electrode, and an upper switching layer overlying the lower switching layer. The lower switching layer comprises a dielectric material doped with a first dopant.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming an interconnect layer over a substrate, wherein the interconnect layer has a first interlayer dielectric layer, a first conductive feature in a first portion of the first interlayer dielectric layer, and a second conductive feature in a second portion of the first interlayer dielectric layer; depositing a dielectric layer over the interconnect layer; removing a first portion of the dielectric layer over the first conductive feature and the first portion of the first interlayer dielectric layer, and remaining a second portion of the dielectric layer over the second conductive feature and the second portion of the first interlayer dielectric layer; and forming a memory structure over the first conductive feature.

Abstract: A method, a device, and an apparatus for controlling laser emission are provided. A secondary emergent laser is emitted at a first time of a detection period. A primary emergent laser emitted at a second time of the detection period is adjusted according to a first detection echo corresponding to the secondary emergent laser.

Abstract: Various embodiments of the present disclosure are directed towards a memory cell including a data storage structure. A top electrode overlies a bottom electrode. The data storage structure is disposed between the top electrode and the bottom electrode. The data storage structure includes a first data storage layer, a second data storage layer, and a third data storage layer. The second data storage layer is disposed between the first and third data storage layers. The second data storage layer has a lower bandgap than the third data storage layer. The first data storage layer has a lower bandgap than the second data storage layer.

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.

Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.