Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.

Abstract: A display panel including a substrate, a first and second driving chips, a circuit board and multiple second signal traces are provided. The first and second driving chips are disposed in a non-display region and located adjacent to each other. The first driving chip has multiple first pins disposed on a first short side and a first long side of the first driving chip. The second driving chip has multiple second pins disposed on a second short side and a second long side of the second driving chip. In the non-display region, a width of the circuit board is smaller than a total width of the first driving chip, the second driving chip and a distance between the first driving chip and the second driving chip, and the circuit board has a plurality of first signal traces. The display panel of the invention decreases an amount of required circuit boards.

Abstract: An optical sensor circuit includes a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The capacitor includes a first terminal and a second terminal. Each transistor includes a first terminal, a control terminal, and a second terminal. The second terminal of the capacitor is coupled to a reference voltage terminal. The first terminals of the third transistor and the fourth transistor are coupled to a first voltage terminal. The second terminal of the fifth transistor is coupled to a readout line.

Abstract: A display panel including a substrate, a first and second driving chips, a circuit board and multiple second signal traces are provided. The first and second driving chips are disposed in a non-display region and located adjacent to each other. The first driving chip has multiple first pins disposed on a first short side and a first long side of the first driving chip. The second driving chip has multiple second pins disposed on a second short side and a second long side of the second driving chip. In the non-display region, a width of the circuit board is smaller than a total width of the first driving chip, the second driving chip and a distance between the first driving chip and the second driving chip, and the circuit board has a plurality of first signal traces. The display panel of the invention decreases an amount of required circuit boards.

Abstract: A backlight module and a display apparatus are provided. The backlight module comprises a back plate, a light source and at least one light-permeable element. The light source disposed on the back plate has at least one light emitting element. The light-permeable element covers the light emitting element, which comprises a light input surface and a light output surface disposed opposite the light input surface. The light input surface faces the light emitting element and has an apex away from the light emitting element. When viewed from a cross section crossing the apex and perpendicular to the back plate, the light input surface has a first curve and a second curve connected to the first curve. A connection point between the first curve and the second curve is an inflection point.

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract: A pixel circuit includes a first capacitor whose two terminals are coupled to a first node and a ground end respectively, a first switch whose two terminals are coupled to a second node and a fourth node respectively, a liquid crystal, a second switch, a pull-up circuit, a pull-down circuit, a second capacitor and a third switch. The first switch is coupled to the first node and a first data input end. The liquid crystal is coupled to the second and a third node. The second switch is coupled to the second node and a second data input end. The pull-up circuit is coupled to the first node and the second node and a node of a high voltage. The pull-down circuit is coupled to the second node, the fourth node and the ground end. The third switch is coupled to the fourth node and the ground end.

Abstract: A liquid-crystal pixel unit includes a storage capacitor, a liquid-crystal capacitor, a data writing circuit, and a source-follower type output circuit. The storage capacitor includes a first electrode and a second electrode. The second electrode is configured to receive a first reference voltage. The liquid-crystal capacitor includes a third electrode and a fourth electrode. The fourth electrode is configured to receive a second reference voltage. The data writing circuit is electrically connected to the first electrode and the third electrode. The data writing circuit is controlled by a control signal to charge a data voltage into the storage capacitor and the liquid-crystal capacitor. The source-follower type output circuit includes an input terminal and an output terminal. The input terminal is electrically connected to the first electrode. The output terminal is electrically connected to the third electrode.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract: A liquid crystal display having photo-sensing input mechanism includes a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a data line for transmitting a data signal, a pixel unit for outputting an image signal according to the first gate signal and the data signal, a readout line for transmitting a readout signal, a photo-sensing input unit and a driving adjustment unit. The photo-sensing input unit is utilized for generating a sensing voltage according to a driving voltage and an incident light signal, and is further utilized for outputting the readout signal according to the sensing voltage and the first gate signal. The driving adjustment unit is employed to provide the driving voltage according to the second gate signal and the incident light signal.

Abstract: A voltage regulator and a control method thereof are provided to dynamically adjust an output voltage. The voltage regulator comprises a plurality of switching transistors and a control circuit. The first end of each switching transistor receives a driving voltage, and the second end of each switching transistor is electrically connected to the end which outputs the output voltage. The input end and the feedback end of the control circuit respectively receive a reference voltage and the output voltage. A plurality of output ends of the control circuit are electrically connected to the control ends of the switching transistors respectively. Switching transistors adjust the output voltage. The control circuit compares the output voltage with the reference voltage, and selectively turns the switching transistors on or off according to the comparison between the output voltage and the reference voltage, to control the output voltage to approach the reference voltage.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.

Abstract: An embodiment of the invention provides an isolation cell for isolating a second power domain from a first power domain. The isolation cell includes an input terminal capable of receiving a first signal of the first power domain, an output terminal capable of outputting an output signal with a predetermined logic state to the second power domain, a first power terminal and a second power terminal. The first power terminal is capable of receiving a voltage from a power source, the power source is different from a first power source of the first power domain, and the isolation cell is powered by the voltage.

Abstract: A liquid crystal display having photo-sensing input mechanism includes a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a data line for transmitting a data signal, a pixel unit for outputting an image signal according to the first gate signal and the data signal, a readout line for transmitting a readout signal, a photo-sensing input unit and a driving adjustment unit. The photo-sensing input unit is utilized for generating a sensing voltage according to a driving voltage and an incident light signal, and is further utilized for outputting the readout signal according to the sensing voltage and the first gate signal. The driving adjustment unit is employed to provide the driving voltage according to the second gate signal and the incident light signal.

Abstract: In a method for transferring data via a digital television (DTV) network and a mobile communication network using an electronic device, the method receives a DTV signal via the DTV network and detects a decode error rate (DER) of the DTV signal at a first frequency. The method further detects the DER of the DTV signal at a second frequency and detects an average signal strength of the mobile communication network when the DER is continuously greater than a first threshold value. The method builds an electronic connection between the electronic device and a multimedia server via the mobile communication network and receives multimedia data from the multimedia server when the DER is continuously greater than a second threshold value and when the average signal strength is continuously greater than a third threshold value.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract: A liquid crystal display having photo-sensing input mechanism includes a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a data line for transmitting a data signal, a pixel unit for outputting an image signal according to the first gate signal and the data signal, a readout line for transmitting a readout signal, a photo-sensing input unit and a driving adjustment unit. The photo-sensing input unit is utilized for generating a sensing voltage according to a driving voltage and an incident light signal, and is further utilized for outputting the readout signal according to the sensing voltage and the first gate signal. The driving adjustment unit is employed to provide the driving voltage according to the second gate signal and the incident light signal.

Abstract: A power management system coupled to a speaker module includes a monitor module for measuring a current signal and a voltage signal of the speaker module to obtain a real-time impedance information of the speaker module; a reception module for receiving a time-domain audio analogy signal to be transformed into a frequency-domain audio digital signal; a prediction module for generating a power prediction information according to an initial audio information, the real-time impedance information and the audio digital signal; a control module for generating a control signal according to the audio digital signal and a human hearing model information; and a power adjustment module for outputting an adjustment audio signal to the speaker module according to the power prediction information, the audio digital signal and the control signal, so as to perform a broadcast operation of the speaker module.