Abstract: An improved clamping fixture for bouncing apparatus to clamp two ends of a resilient stem of a bouncing apparatus includes two coupling members and two anchor members. The two coupling members are made from plastics and have respectively a first latch member and a second latch member to form a clamping space, and anchor bosses on two outer sides pivotally engageable with the anchor members. The two coupling members have coupling forces to clamp the two ends of the resilient stem, and the two anchor members are coupled on the upper end and lower end of the bouncing apparatus. The resilient stem can be positioned securely at two ends of the bouncing apparatus to facilitate bouncing operation without being scraped, damaged or fractured. Durability is greater.

Abstract: A shift register circuit includes a shift register unit and a buffer. The buffer is coupled to the output terminal of the shift register unit to delay the output signal from the shift register unit. The overlapped voltage of two output signals from two adjacent shift register units can be reduced.

Abstract: This invention relates to a driving circuit for flat panel displays wherein the driving circuit is disposed on a flat panel display panel. The circuit has a plurality of signal lines, at least one buffer unit for inverting a scanning signal, a plurality of switch units and an active area (display area). The plurality of signal lines supplies a plurality of analogous video signals to the plurality of switch units. The unit for inverting a scanning signal generates at least a scanning signal which is then outputted to the plurality of switch units. The analogous video signal so received is transformed into the active-matrix display area by controlling the operation of the plurality of switch units.

Abstract: An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.

Abstract: The system for display test includes a driving circuit having integrated circuit (IC) pads on the substrate and the IC pads are electrically connected to the signal lines, respectively. And the first switches are between the first test pads and the IC pads, wherein the number of the first test pads is less than the number of the IC pads.

Abstract: A display device has a display panel, which includes a plurality of IC pads, a plurality of data lines, a selector, a plurality of switches and a test pad. The IC pads are connected to the data lines through the selector. The data lines are electrically connected to a corresponding pixel circuit. The IC pads are connected to the test pad via the corresponding switch. The switches are sequentially turned on to sequentially transmit a voltage to the corresponding pixel circuit through the test pad.

Abstract: A display driving circuit having a plurality of driving stages and driving lines is provided. The driving stages are electrically coupled in serial, and each of the driving stages comprises a conducting path for transmitting an electric signal from the previous driving stage to the next driving stage via the current driving stage. Each of the driving lines respectively corresponds to a driving stage and electrically connects to an output terminal of the corresponding driving stage. The display driving circuit is characterized in that a redundant device is only installed in one part of the driving stages. The redundant device is capable of supplying an extra conducting path to transmit an electric signal from the previous driving stage to the next driving stage via the current driving stage while the original conducting path in the corresponding driving stage is broken.

Abstract: A shift register circuit includes a shift register unit and a buffer. The buffer is coupled to the output terminal of the shift register unit to delay the output signal from the shift register unit. The overlapped voltage of two output signals from two adjacent shift register units can be reduced.

Abstract: The system for display test includes a driving circuit having integrated circuit (IC) pads on the substrate and the IC pads are electrically connected to the signal lines, respectively. And the first switches are between the first test pads and the IC pads, wherein the number of the first test pads is less than the number of the IC pads.

Abstract: A polishing pad and fabricating method thereof includes a polishing pad body and at least a compressibility-aiding stripe. The compressibility-aiding stripe is buried in the polishing pad body and has a larger compressibility than that of the polishing pad body.

Abstract: A clock signal amplifying method and driving stage for LCD driving circuit is provided. The driving stage includes a clock input, a level shifter, and an output buffer. Firstly, the clock input receives a cock signal oscillating between a high original level and a low original level. Thereafter, a level shifter is biased at a high target level and a low target level, and amplifies the clock signal to a relay signal, which oscillates between a high relay level and a low relay level. Lastly, the output buffer is biased at the high relay level and the low relay level for amplifying the relay signal to a target signal, which oscillates between the high target level and the low target level.

Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.

Abstract: A display device has a pixel array, a plurality of data buses and a drive circuit. The pixel array has a plurality of data lines and a plurality of pixels. The pixels are electrically coupled to the data lines, and these data lines are electrically coupled to these data buses. The drive circuit receives a plurality of image data sequentially and transforms the image data into pixel voltages, which are outputted from corresponding output terminals.

Abstract: A bootstrap inverter circuit, consisting of transistors of the same type, comprises a first transistor, a second transistor, a voltage clamp circuit and an output end. The voltage clamp circuit, having a first node and a second node, controls the voltage of a gate of the second transistor. A gate and a first end of the first transistor are connected to a power source. A gate of the second transistor is connected to the second node of the voltage clamp circuit. A first end of the second transistor is connected to the power source. A second end of the second transistor is connected to the output end. The first node of the voltage clamp circuit is connected to the power source. The second node of the voltage clamp circuit is connected to a second end of the first transistor.

Abstract: An improved dynamic shift register circuit is disclosed. A circuit design is provided to minimize overlapping between two adjacent output pulses in the dynamic shift register circuit. In an application of analog sample-and-hold circuit, the circuit design effectively improves a distortion of sampled data caused by significant overlapping of two adjacent output pulses as control signals.

Abstract: A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The disable circuit is capable of being coupled with a dynamic shift register unit having an input for receiving an input pulse and an output for outputting a shifted pulse. The disable circuit generates an output signal during an input pulse period or an output pulse period for the dynamic shift register unit, wherein the input pulse period and the output pulse period are responsive to a first input pulsed signal from the first input and a second input pulsed signal from the second input, respectively.

Abstract: A display device has a display panel, which includes a plurality of IC pads, a plurality of data lines, a selector, a plurality of switches and a test pad. The IC pads are connected to the data lines through the selector. The data lines are electrically connected to a corresponding pixel circuit. The IC pads are connected to the test pad via the corresponding switch. The switches are sequentially turned on to sequentially transmit a voltage to the corresponding pixel circuit through the test pad.

Abstract: A driving method of liquid crystal display. Voltage levels of pre-charging signals applied to storage electrodes vary before scan signals are applied to scan lines. Partial response voltage of the variations in voltage levels of pre-charging signals are respectively coupled to storage capacitors within pixels by capacitors. When the scan signals are applied to the scan lines, voltage swings of the pixel capacitors charged by image data on data lines decrease, rapidly charging the pixels.

Abstract: Pixel structures and methods for fabricating the same are provided. The pixel structure comprises a thin film transistor formed on a substrate. The thin film transistor comprises a gate electrode and an active layer. The active layer comprises a source region and a drain region doped with a first dopant. A capacitor is formed on the substrate. The capacitor comprises a lower electrode and an upper electrode. The lower electrode is doped with a second dopant electrically connecting the source region. The first dopant and the second dopant are of different types.

Abstract: A precharge system for active matrix display devices having data and scan lines, pixels, and first and second voltage sources. The precharge system comprises a precharge circuit having first transistors, with gate electrode and drain electrode connected to function as a diode, of which a first terminal is coupled to the first voltage source, a second transistor of which a first terminal is coupled to the second terminals of the first transistors, a second terminal is coupled to the data lines, and a control terminal receives a positive precharge signal, third transistors, connected to function as a diode, of which a first terminal is coupled to the second voltage source, and a fourth transistor of which a first terminal is coupled to the second terminals of the third transistors, a second terminal is coupled to the corresponding data lines, and a control terminal receives a negative precharge signal.