Patents by Inventor Sheng An Tsai

Sheng An Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942467
    Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Sheng Chen, Yi-Jing Li, Chia-Ming Hsu, Wan-Lin Tsai, Clement Hsingjen Wann
  • Patent number: 11942795
    Abstract: A multi-antenna system for harvesting energy and transmitting data includes an energy storing unit, antenna transmission units, and a load unit. Each antenna transmission unit includes an antenna module, a splitting module, an energy generation module, and a data processing module. The splitting module splits a wireless signal received by the antenna module into a first splitting signal and a second splitting signal and transmits the first splitting signal to an energy generation module to convert the first splitting signal into electrical energy stored in an energy storing unit and provided to the data processing module. The energy storing unit provides the electrical energy for the load unit. The data processing module receives one of the second splitting signals, converts it into a control signal, and transmits the control signal to the load unit. The load unit operates according to the control signal.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: March 26, 2024
    Assignee: Netronix, Inc.
    Inventors: Fang Ming Tsai, You Wei Zhang, Jun Sheng Lin
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Publication number: 20240097762
    Abstract: A method pertaining to channel state information (CSI) reporting for multiple transmission/reception-points (multi-TRP) in next-generation mobile communications involves a user equipment (UE) generating a CSI report for multiple TRPs in communications with the UE. Additionally, the method also involves the UE transmitting the CSI report to one or more of the multiple TRPs using one or multiple CSI reporting resources.
    Type: Application
    Filed: February 5, 2021
    Publication date: March 21, 2024
    Inventors: Gyu Bum KYUNG, Lung-Sheng TSAI
  • Publication number: 20240098953
    Abstract: This application discloses electromagnetic energy mitigation assemblies and automotive vehicle components comprising the electromagnetic energy mitigation assemblies. An electromagnetic energy mitigation assembly includes a first electrically conductive layer and a second electrically conductive layer. First and second permalloy layers are along respective first and second opposite sides of the first electrically conductive layer. Third and fourth permalloy layers are along respective third and fourth opposite sides of the second electrically conductive layer. An electromagnetic noise suppression layer is sandwiched between the second and third permalloy layers. An automotive vehicle component includes an electromagnetic energy mitigation assembly configured to be positioned relative to one or more batteries of an automotive vehicle for providing electromagnetic shielding for the one or more batteries. The electromagnetic energy mitigation assembly includes a first electrically conductive layer.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Tsang-I TSAI, Yunxi SHE, Dong-Xiang LI, Jie-Sheng CHEN, Min-Wei HSU
  • Publication number: 20240096787
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240090340
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Ming-Che Ku, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang
  • Patent number: 11927312
    Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 12, 2024
    Assignee: Innolux Corporation
    Inventors: Chin-Chia Huang, Chieh-Ying Chen, Jia-Huei Lin, Chin-Tai Hsu, Tzu-Chien Huang, Fu-Sheng Tsai
  • Publication number: 20240080071
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE determines a first codebook and a second codebook associated with a first antenna panel and a second antenna panel. The UE receives, from a base station, a first indication for constructing, based on the first codebook, a first precoder to be applied to the first antenna panel. The UE receives, from the base station, a second indication for constructing, based on the second codebook, a second precoder to be applied to the second antenna panel. The UE transmits, through the first antenna panel, first signals generated according to the first precoder and directed to the base station. The UE transmits, through the second antenna panel, second signals generated according to the second precoder and directed to a wireless device.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Inventor: Lung-Sheng Tsai
  • Publication number: 20240080072
    Abstract: A UE receives a first precoder indication from a base station. The first precoder indication indicates a first precoder for a first antenna panel. The UE receives a second precoder indication from the base station. The second precoder indication indicates a second precoder for a second antenna panel. The UE receives an indication of first time-frequency resources from the base station for communicating via the first antenna panel. The UE receives an indication of second time-frequency resources from the base station for communicating via the second antenna panel. The UE transmits first signals generated according to the first precoder indication through the first antenna panel on the first time-frequency resources. The UE transmits second signals generated according to the second precoder indication through the second antenna panel on the second time-frequency resources.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Inventor: Lung-Sheng Tsai
  • Publication number: 20240076797
    Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Inventors: Hong-Huei Huang, Benjamin Michael Meyer, Chun-Sheng Wu, Wei-Chen Chou, Chen-Yi Lin, Feng-Chien Tsai
  • Publication number: 20240079051
    Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 7, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Tuo-Hung Hou, Fu-Cheng Tsai, Jian-Wei Su, Kuo-Hua Tseng
  • Publication number: 20240080070
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE transmits a capability report to a base station. The capability report indicates one or more capabilities of an aggregated mobile terminal (MT) formed by the UE and one or more devices each being a component device. The UE receives configurations of an initial set of reference signals from the base station. The configurations respond to the one or more capabilities. The UE transmits an initial report to the base station. The initial report indicates codebook parameters. The UE receives codebook configurations of a codebook from the base station. The codebook is for generating a downlink precoder matrix for CSI reporting or for generating an uplink precoder matrix for uplink transmission.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Inventor: Lung-Sheng Tsai
  • Patent number: 11923455
    Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
  • Publication number: 20240071665
    Abstract: A wheel control mechanism includes a support base, a wheel module, a first magnetic module and a second magnetic module. The wheel module, the first magnetic module and the second magnetic module are installed on the support base. The first magnetic module generates a magnetic attractive force to attract a metal ratchet of the wheel module. By adjusting the position of the second magnetic module relative to the first magnetic module, the strength of the magnetic attractive force is changed. Consequently, the rotation of the wheel module results in a tactile feel or does not result in the tactile feel.
    Type: Application
    Filed: September 14, 2022
    Publication date: February 29, 2024
    Inventors: Chun-Nan Su, Chun-Che Wu, Sheng-An Tsai, Ming-Hao Hsieh, Li-Kuei Cheng
  • Publication number: 20240069583
    Abstract: A control circuit including a storage circuit, a voltage detection circuit, a processing circuit, and a wake-up circuit is provided. The storage circuit includes a register and stores a program code. The voltage detection circuit detects an external voltage. The processing circuit accesses the register in response to the external voltage reaching a first predetermined voltage. The processing circuit enters a power-down mode in response to the external voltage reaching a second predetermined voltage. In the power-down mode, the processing circuit stops accessing the register. The wake-up circuit determines whether a wake-up event occurs. In response to the wake-up event, the wake-up circuit directs the processing circuit to exit the power-down mode and enter an operation mode. In response to there being no wake-up event, the processing circuit stays in the power-down mode. In the operation mode, the processing circuit executes the program code.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Chieh-Sheng TU, Te-Tsoung TSAI, Ta-Chin CHIU
  • Publication number: 20240072987
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives downlink data signals from a base station on a first set of frequency resources in a specific slot. The UE transmits uplink data signals directed to the base station on a second set of frequency resources to a repeater in the same specific slot.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 29, 2024
    Inventor: Lung-Sheng Tsai
  • Publication number: 20240069173
    Abstract: An output stage circuit, comprising: a current source circuit; an output switch circuit, comprising at least one output switch, coupled to the current source circuit, wherein an output current flows through a target circuit when the output switch circuit is conducted; at least one bias capacitor, coupled to the current source circuit; and a bias switch circuit, configured to receive a bias voltage, comprising at least one bias switch, coupled to the bias capacitor and the current source circuit, wherein the bias voltage charges the bias capacitor when the bias switch circuit is conducted. The present invention further discloses a DAC applying the output stage circuit and a TOF system applying the DAC. The conventional kick back issue can be improved by the mechanism provided by the present invention.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Yueh-Lin Chung, Tso-Sheng Tsai
  • Patent number: 11915512
    Abstract: A three-dimensional sensing system includes a plurality of scanners each emitting a light signal to a scene to be sensed and receiving a reflected light signal, according to which depth information is obtained. Only one scanner executes transmitting corresponding light signal and receiving corresponding reflected light signal at a time.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: February 27, 2024
    Assignee: Himax Technologies Limited
    Inventors: Ching-Wen Wang, Cheng-Che Tsai, Ting-Sheng Hsu, Min-Chian Wu